TMP86FS23UG datasheet(190/252 Pages) TOSHIBA

190 / 252 page

Page 178

17. Multiply-Accumulate (MAC) Unit

17.3 Control

TMP86FS23UG

17.2.2 Status Register

The status register contains flags to indicate the operation status of the MAC unit and the calculation result.

17.2.3 Multiplier data Register

The data written to this register is calculated as a multiplier.

17.2.4 Multiplicand data Register

The data written to this register is calculated as a multiplicand.

17.2.5 Result Register

The calculation result is stored in this register.

17.2.6 Addend Register

The data written to this register is calculated as an addend in a multiply-accumulate operation. An addend

must be written to this register while calculation is not being performed (CALC = “0”).

17.3 Control

Note 1: Setting RCLR to “1” causes the result, addend, and status registers to be initialized. The multiplier, multiplicand, and com-

mand registers remain the same as before. (RCLR is automatically cleared to “0” one machine cycle after it is set to “1”.)

Note 2: Writing to CMOD (including an overwrite) makes no changes to the status, multiplier, multiplicand, result, and addend reg-

isters.

Note 3: Before changing the arithmetic mode, be sure to check that calculation is not being performed (CALC = “0”).

Note 4: Clearing the result register with RCLR is possible only when calculation is not being performed (CALC = “0”). (RCLR can-

not be set to “1”during calculation.)

Note 5: Bits 6 to 4 are always read as “1”. ( “0” cannot be written.)

Command Register

MACCR

(0FA4H)

543

RCLR

“1”

CMOD

EMAC

(Initial value: 0111 0000)

RCLR

Result register clear

0: -(Keeps the value of the result register.)

1: Clears the result register. (This bit is automatically cleared to “0” one

machine cycle after it is set to “1”.)

R/W

CMOD

Arithmetic mode

000: Unsigned multiply (16 bits

× 16 bits)

001: Unsigned multiply-accumulate (16 bits

× 16 bits + 32 bits)

010: Signed multiply (16 bits

× 16 bits)

011: Signed multiply-accumulate (16 bits

× 16 bits + 32 bits)

1**: Reserved

EMAC

MAC unit control

0: Disables the MAC unit.

1: Enables the MAC unit.

Status Register

MACSR

(0FA5H)

543

“1”

CARF

ZERF

SIGN

OVRF

CALC

(Initial value: 1110 0000)

TMP86FS23UG Datasheet(PDF) 190 Page - Toshiba Semiconductor

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