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TMP86FS23UG Datasheet(PDF) 194 Page - Toshiba Semiconductor

Part # TMP86FS23UG
Description  8 Bit Microcontroller
PDF  252 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP86FS23UG Datasheet(HTML) 194 Page - Toshiba Semiconductor

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Page 182
17. Multiply-Accumulate (MAC) Unit
17.6 Status Flags
TMP86FS23UG
causes the result and addend registers to be cleared. After calculation is completed, the contents of the result
register are automatically stored in the addend register. Thus, if the contents of the addend register are not
changed, the result of the previous multiply-accumulate operation is used as an addend for the next calculation.
Note 1: Be sure to write to the addend register when calculation is not being performed (CALC = “0”).
Note 2: Writing to the addend register changes the contents of the result register. Thus, read from the result register
before writing to the addend register.
17.5.4 Signed Multiply-Accumulate Mode
Setting the MACCR<CMOD> field in the command register to “011B” places the MAC unit in signed mul-
tiply-accumulate mode. In this mode, bit 15 in the multiplier and multiplicand register is each treated as the
sign bit.
Calculation is started automatically by writing a multiplier to the multiplier register (MPLDRH, MPLDRL)
and then writing a multiplicand to the lower byte (MPCDRL) and upper byte (MPCDRH) of the multiplicand
register in this order. First, the multiplicand and multiplicand are multiplied. Then, the contents of the addend
register are added to the product. The sum is stored as signed 32-bit data in the result register (RCALDR4 to
RCALDR1). The sign of the result varies as shown in Table 17-4. As in the case of unsigned multiply-accumu-
late mode, any addend can be written to the addend register when calculation is not being performed.
Note: In signed multiply-accumulate mode, bit 31 in the addend register is treated as the sign bit.
17.5.5 Valid Numerical Ranges
Table 17-5 shows the numerical range that can be handled in each arithmetic mode.
17.6 Status Flags
The status register MACSR contains the following five flags. OVRF, CARF, SIGN, and ZERF are programmed
when calculation is completed, and these flags are not affected by a read from the status register.
1. Operation status flag (CALC)
2. Overflow flag (OVRF)
3. Carry flag (CARF)
4. Sign flag (SIGN)
5. Zero flag (ZERF)
Table 17-4 Signs Used in Sgined Multiply-Accumulate Mode
Sign of Product
Sign of Addend
Sign (bit 31) of Calculation Result
When OVRF = “0”
When OVRF = “1”
00
0
1
01
“1” when sum < 0
“0” when sum
≥ 0
–
10
“1” when sum < 0
“0” when sum
≥ 0
–
11
1
0
Table 17-5 Valid Numerical Ranges in Decimal (with hexadecimal shown in brackets)
Mode
Multiplier/Multiplicand
Addend
Sum
Unsigned multiply
0 to 65535
(0000H to FFFFH)
–
0 to 4294836225
(00000000H to FFFE0001H)
Signed multiply
-32768 to 32767
(8000H to 7FFFH)
–
-1073709056 to 1073741824
(C0008000H to 40000000H)
Unsigned multiply-
accumulate
0 to 65535
(0000H to FFFFH)
0 to 4294967295
(00000000H to FFFFFFFFH)
0 to 4294967295
(00000000H to FFFFFFFFH)
Signed multiply-
accumulate
-32768 to 32767
(8000H to 7FFFH)
-2147483648 to 2147483647
(80000000H to 7FFFFFFFH)
-2147483648 to 2147483647
(80000000H~7FFFFFFFH)



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