TMP86FS23UG datasheet(193/252 Pages) TOSHIBA

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Page 181

TMP86FS23UG

Note 4: When the MAC unit is enabled (EMAC = “1”), if the operation mode is changed to IDLE0/1/2, SLOW1/2, or STOP mode,

the command register (MACCR) is initialized and its contents are discarded. Thus, program the MACCR again after each

of these operation modes is exited.

17.5 Arithmetic Modes

The following four arithmetic modes are available:

1. Unsigned multiply (16 bits

× 16 bits)

2. Signed multiply (16 bits

× 16 bits)

3. Unsigned multiply-accumulate (16 bits

× 16 bits + 32 bits)

4. Signed multiply-accumulate (16 bits

× 16 bits + 32 bits)

17.5.1 Unsigned Multiply Mode

Setting the MACCR<CMOD> field in the command register to “000B” places the MAC unit in unsigned

multiply mode. In this mode, the values of the multiplier and multiplicand registers are each treated as 16-bit

data for calculation.

Calculation is started automatically by writing a multiplier to the multiplier register (MPLDRH, MPLDRL)

and then writing a multiplicand to the lower byte (MPCDRL) and upper byte (MPCDRH) of the multiplicand

RCALDR1). (The previous calculation result is cleared.)

17.5.2 Signed Multiply Mode

Setting the MACCR<CMOD> field in the command register to “010B” places the MAC unit in signed mul-

tiply mode. In this mode, bit 15 in the multiplier and multiplicand registers is each treated as the sign bit.

Calculation is started automatically by writing a multiplier to the multiplier register (MPLDRH, MPLDRL)

and then writing a multiplicand to the lower byte (MPCDRL) and upper byte (MPCDRH) of the multiplicand

RCALDR1). (Bit 31 contains the sign, and the previous calculation result is cleared.) The sign of the calcula-

tion result varies depending on the signs of the multiplier and multiplicand, as shown in Table 17-3.

17.5.3 Unsigned Multiply-Accumulate Mode

Setting the MACCR<CMOD> field in the command register to “001B” places the MAC unit in unsigned

multiply-accumulate mode. In this mode, the values of the multiplier and multiplicand registers are each

treated as 16-bit data for calculation.

Calculation is started automatically by writing a multiplier to the multiplier register (MPLDRH, MPLDRL)

and then writing a multiplicand to the lower byte (MPCDRH) and upper byte (MPCDRH) of the multiplicand

ister are added to the product. The sum is stored as 32-bit data in the result register.

In unsigned multiply-accumulate mode, any addend can be written to the addend register when calculation is

not being performed. If, for example, A

× B is executed after arbitrary data C is written to the addend register,

the result of A

× B + C is stored in the result register (RCALDR4 to RCALDR1). Setting the RCLR bit to “1”

Table 17-3 Signs Used in Singed Multiply Mode

Sign of Multiplier

Sign of Multiplicand

Sign of Calculation Result

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