TMP86FS23UG datasheet(192/252 Pages) TOSHIBA

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Page 180

17. Multiply-Accumulate (MAC) Unit

17.4 Register Description

TMP86FS23UG

Note 1: In signed arithmetic mode, bit 31 is treated as the sign bit.

Note 2: Writing to the addend register changes the contents of the result register. Thus, read from the result register before writing

to the addend register.

17.4 Register Description

17.4.1 EMAC

Setting MACCR<EMAC> to “1” enables the MAC unit. Once enabled, the MAC unit remains enabled until

it is disabled.

17.4.2 CMOD

The MACCR<CMOD> is used to specify the arithmetic mode.

Calculation is started automatically when data is written to both the lower byte (MPCDRL) and upper byte

(MPCDRH) of the multiplicand register in this order. Thus, the multiplier register (MPLDRH, MPLDRL) must

be set before the multiplicand register. When calculation is completed, the result is stored in the result register

(RCALDR4 to RCALDR1).

The arithmetic mode is valid until the CMOD field is changed. Note that if the operation mode is changed to

IDLE0/1/2, SLOW1/2, or STOP mode, CMOD is initialized.

During calculation, the next data can be written to the multiplier and multiplicand registers only once. Do not

write to these registers more than once. Whether or not calculation is in progress can be checked by reading the

MACSR<CALC> flag.

Note 1: Before changing the arithmetic mode, ensure that calculation is not being performed (CALC = “0”).

Note 2: Writing to the CMOD field (including an overwrite) makes no changes to the status, multiplier, multiplicand,

result, and addend registers. Thus, to clear the status, result, and addend registers after a change of the

arithmetic mode, set the RCLR bit to “1”.

17.4.3 RCLR

When calculation is not being performed (CALC = “0”), setting MACCR<RCLR> to “1” causes the result,

addend, and status registers to be initilized. (The multiplier and multiplicand registers remain the same as

before.) RCLR is automatically cleared to “0” one machine cycle after it is set to “1”

Note:When calculation is in progress (CALC = “1”), RCLR cannot be set to “1”. (The instruction to set it to “1” is

invalid.)

As shown in Table 17-2, the state of each register changes when: the MAC unit is disabled (EMAC = “0”);

the result register is cleared (RCLR = “1”); or the operation mode is changed.

Note 1: The multiplier, multiplicand, and addend registers can be written to only when the MAC unit is enabled (EMAC = “1”).

Note 2: When writing to the multiplicand register, be sure to write to the lower byte (MPCDRL) first and then to the upper byte

(MPCDRH).

Note 3: RCLR can be written to only when calculation is not being performed (CALC = “0”).

Table 17-2 Effects of the EMAC and RCLR Bits on the MAC Registers

EMAC = “0” (Disable)

RCLR = “1” (register clear)

IDLE0/1/2, SLOW1/2, or

STOP Mode

Command register (MACCR)

Bits other than EMAC remain

the same as before

Bits other than RCLR remain the same as

before. RCLR is cleared to “0” after one

machine cycle.

Initialized

Status register (MACSR)

Initialized

Multiplier data register (MPLDRH, MPLDRL)

Initialized

Remains the same as before

Initialized

Multiplicand data register (MPCDRH, MPCDRL)

Initialized

Remains the same as before

Initialized

Result register (RCALDR4 to RCALDR1)

Initialized

Addend register (MADDR4 toMADDR1)

Initialized

TMP86FS23UG Datasheet(PDF) 192 Page - Toshiba Semiconductor

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