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A Product Line of

Diodes Incorporated

PI6CB332016A

November 2024

© 2024 Copyright Diodes Incorporated. All Rights Reserved.

PI6CB332016A

Document Number DS45931 Rev 3-2

www.diodes.com

This interface consists of DATA, CLK and SHFT_LD# pins. When the SHFT_LD# pin is high, the rising edge of CLK can shift DATA

into the shift register. After shifting data, the falling edge of SHFT_LD# clocks the shift register contents to the Output register.

When the SBI is enabled, DATA, CLK, and SHFT_LD# are enabled on OE9#, OE5# and OE13# respectively. Additionally, SMBus

registers for masking off the disable function of the shift register (0 value of a bit) become active. When set to a one, the mask register

forces its respective output to 'enabled.' This prevents accidentally disabling critical outputs when using the SBI.

An SMBus read back bit in Byte 4 indicates which output enable control interface is enabled.

When the SBI is enabled, and power has been applied, the SBI is active, even if the PWRGD/PWRDN# pin indicates the part is in

power down. This allows loading the shift register and transferring the contents to the output register before the assertion of PWRGD.

Note that the mask registers are part of the normal SMBus interface and cannot be accessed when the PWRGD/PWRDN# is low.

Figure 2 provides a functional description of the SBI.

The SBI and the traditional SMBus output enable registers both default to the 'output enabled' state at power-up. The mask registers

default to zero at power-up, allowing the shift bits to disable their respective output. See Figure 2.

Mask 0

Mask 1

Mask 15

Byte 8

Byte 9

SMBus Mask Registers

(Default is ‘0’)

To Output Logic

SBI_out

OE0

OE15

O

IO

D

OE1

O

IO

D

O

IO

D

D0

D1

D15

to D2

from D14

DATA

CLK

SHFT_LD#

Output

Register

(Default is 1)

Shift

Register

Side-Band Interface

Figure 2. Side Band Interface Control Logic Description

Figures 3 shows the basic timing of the side-band interface. The SHFT_LD# pin goes high to enable the CLK input. Next, the rising

edge of CLK clocks enable DATA into the shift register. After the 16th clock for output 16, stop the clock low and drive the SHFT_LD#

pin low. The falling edge of SHFT_LD# clocks the shift register contents to the output register, enabling or disabling the outputs. Al-

ways shift 16 bits of data into the shift register to control the outputs.

Side-Band Interface