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A Product Line of

Diodes Incorporated

PI6CB332016A

November 2024

© 2024 Copyright Diodes Incorporated. All Rights Reserved.

PI6CB332016A

Document Number DS45931 Rev 3-2

www.diodes.com

Applications Information

Power Down Tolerant Pins

Pins that are Power Down Tolerant (PDT) can be driven by voltages as high as the normal VDD of the chip, even though VDD is not

present (the device is not powered). There will be no ill effects to the device and it will power up normally. This feature supports disag-

gregation, where the PI6CB3320xx may be on one circuit board and devices that interface with it are on other boards. These boards may

power up at different times, driving pins on the PI6CB3320xx before it has received power.

Flexible Startup Sequencing

PI6CB3320xx devices support Flexible Startup Sequencing (FSS), IN+/- pins are PDT. FSS allows application of CLKIN at different

times in the device/system startup sequence. FSS is an additional feature that helps the system designer manage the impact of disag-

gregation. Table shows the supported sequences; that is, the PI6CB3320xx devices can have CLKIN running before VDD is applied, and

can have VDD applied and sit for extended periods with no input clock.

Loss of Signal and Automatic Clock Parking

The PI6CB3320xx buffers have a Loss of Signal (LOS) circuit to detect the presence or absence of an input clock. The LOS circuit drives

the open-drain LOS# pin (the “#” suffix indicates “bar”, or active-low) and sets the LOS_EVT bit in the SMBus register space. There are

two slightly different LOS# pin behaviors at power up. Figure 4 and Figure 5 show the LOS# de-assertion timing for the 4, 8, 13, 16 and

20-output buffers. CLKIN is represented differentially in Figure 4 and Figure 5.

a+

b+

1st Clock

Release

c+

d

LOSDeassert

typ

e+

f

LOSDeassert

max

VDD

CLKIN

LOS#

Figure 4. LOS# De-assert Timing for 4/8/13/16 Outputs

Note: The LOS circuit on the 16-output buffer requires a CLKIN edge to release the LOS# pin after power up. So, the LOS# pin will be high until the first clock edge after

power up.

c+

d

LOSDeassert

typ

e+

f

LOSDeassert

max

VDD

CLKIN

LOS#

Figure 5. LOS# De-assert Timing for 20 Outputs

Figure 5 shows the LOS# de-assertion timing for the 20-output buffers. LOS# on the 20-output buffers defaults to low at power up.