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PI6CB332016A Datasheet(PDF) 2 Page - Diodes Incorporated

Part # PI6CB332016A
Description  16-Output Low-Power Fanout Clock Buffer for PCIe 6.0 Application
PDF  27 Pages
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Manufacturer  DIODES [Diodes Incorporated]
Direct Link  http://www.diodes.com
Logo DIODES - Diodes Incorporated

PI6CB332016A Datasheet(HTML) 2 Page - Diodes Incorporated

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A Product Line of
Diodes Incorporated
PI6CB332016A
November 2024
© 2024 Copyright Diodes Incorporated. All Rights Reserved.
PI6CB332016A
Document Number DS45931 Rev 3-2
www.diodes.com
Pin Number
Pin Name
Type
Description
1
LOS#
Output
Open
Drain
Open drain output, needs external pull up, Low output indicates loss
of input clock signal, PDT.
2
SLEWRATE_SEL
Input
CMOS Input to select default slew rate of the outputs. 0 = Slow Slew Rate, 1 =
Fast Slew Rate. Internal pull up.
3
SADR1_tri
Input
Tri-level
SMBus address bit. This is a tri-level input that works in conjunction
with SADR0_TRI pin, to decode SMBus addresses. It has internal
pull-up/down resistors to bias to VDD/2. See the SMBus Address
Selection table.
4
SADR0_tri
Input
Tri-level
SMBus address bit. This is a tri-level input that works in conjunction
with SADR1_TRI pin, to decode SMBus addresses. It has internal
pull-up/down resistors to bias to VDD/2. See the SMBus Address
Selection table.
LOS#
52
1
2
SLEWRATE_SEL
3
SADR1_TRI
4
SADR0_TRI
5
SDATA
6
SCLK
7
VDDDIG
8
IN+
9
IN-
10
OE15#
11
OE14#
12
VDDCLK
13
Q15+
14
Q15-
15
Q14+
16
Q14-
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53
49
51 50
OE5#_SBI_CLK
Q5-
Q5+
OE6#
VDDCLK
Q6-
Q6+
Q7-
Q7+
OE7#
Q8-
Q8+
OE8#
Q9-
Q9+
VDDCLK
EPAD
GND
Pin Configuration
Pin Description



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