PIC16F18323-ESLASHSLSQTP datasheet(101/442 Pages) MICROCHIP

101 / 442 page

 2015 Microchip Technology Inc.

Preliminary

DS40001799A-page 101

PIC16(L)F18313/18323

8.2.1

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

External Reset input on MCLR pin, if enabled.

BOR Reset, if enabled.

POR Reset.

Watchdog Timer, if enabled.

Any external interrupt.

Interrupts by peripherals capable of running

during Sleep (see individual peripheral for more

information).

The first three events will cause a device Reset. The

last three events are considered a continuation of

program execution. To determine whether a device

Reset or wake-up event occurred, refer to Section 5.11,

Determining the Cause of a Reset.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEP

instruction, the device will then call the Interrupt

Service Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes-up from

Sleep, regardless of the source of wake-up.

8.2.2

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source, with the exception of the clock

switch interrupt, has both its interrupt enable bit and

interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP

instruction

- SLEEP instruction will execute as a NOP

- WDT and WDT prescaler will not be cleared

-TO bit of the STATUS register will not be set

-PD bit of the STATUS register will not be

cleared

• If the interrupt occurs during or after the

execution of a SLEEP instruction

- SLEEP instruction will be completely

executed

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

-TO bit of the STATUS register will be set

-PD bit of the STATUS register will be cleared

Even if the flag bits were checked before executing a

SLEEP

instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

FIGURE 8-2:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN(1)

CLKOUT(2)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

Instruction

Fetched

Instruction

Executed

PC + 1

PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Forced NOP

PC + 2

0004h

0005h

Forced NOP

TOST(3)

PC + 2

Note

External clock. High, Medium, Low mode assumed.

CLKOUT is shown here for timing reference.

TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes.

GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

PIC16F18323-E/SLSQTP Datasheet(PDF) 101 Page - Microchip Technology

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