SLG51002 datasheet(4/37 Pages) RENESAS

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SLG51002

PMIC with High PSRR, Low Noise, Multi-Output LDOs

and Integrated Load Switches

Datasheet

Revision 3.11

25-Jul-2023

CFR0011-120-00

4 of 36

Block Diagram

SLG51002

Sup plies

LDO 1

VOUT 1.2 V to 3.75 V

IOUT_MAX 500 mA

LDO6

VOUT 0.5 V to 1.4 V

IOUT_MAX 1 A

Loa d Switch 6

RON 40 mΩ

Reference

I2C pin s and

Sup ply Controller

OTP

0. 45 µF

VO UT1

VDD

Digital Con tro l

LDO_CORE

4 µF

VO UT6

VI N6

VIN 0.8 V to 1.5 V

GPIO5(SDA)

GPI6(SCL)

LDO7

VOUT 0.5 V to 1.4 V

IOUT_MAX 1 A

Loa d Switch 7

RON 40 mΩ

4 µF

VO UT7

LDO8

VOUT 0.5 V to 1.4 V

IOUT_MAX 1.3 A

Loa d Switch 8

RON 40 mΩ

4 µF

VO UT8

VI N7

VIN 0.8 V to 1.5 V

VI N8

VIN 0.8 V to 1.5 V

VI N1_2

VIN 1.7 V to 5.0 V

0. 45 µF

VOUT2

0. 45 µF

VO UT3

VI N3

VIN 1.7 V to 5.0 V

LDO4

VOUT 1.2 V to 3.75 V

IOUT_MAX 500 mA

Loa d Switch 4

IOUT_MAX 800 mA

RON 150 mΩ

0. 45 µF

VO UT4

VI N4

VIN 1.7 V to 5.0 V

LDO5

VOUT 1.2 V to 3.75 V

IOUT_MAX 500 mA

Loa d Switch 5

IOUT_MAX 800 mA

RON 150 mΩ

0. 45 µF

VO UT5

VI N5

VIN 1.7 V to 5.0 V

VDDIO

GPIO1 to 4

IOs

LDO2

VOUT 1.2 V to 3.75 V

IOUT_MAX 500 mA

LDO3

VOUT 1.2 V to 3.75 V

IOUT_MAX 500 mA

Gre enPAK

Resources

Figure 1: Block Diagram

SLG51002 Datasheet(PDF) 4 Page - Renesas Technology Corp

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