SLG51002 datasheet(7/37 Pages) RENESAS

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SLG51002

PMIC with High PSRR, Low Noise, Multi-Output LDOs

and Integrated Load Switches

Datasheet

Revision 3.11

25-Jul-2023

CFR0011-120-00

7 of 36

Pin No.

Name

Signal

Name

Function

Input Options

Output Options

VIN6

Controller and power

FET supply voltage for

LDO6.

VIN7

Controller and power

FET supply voltage for

LDO7.

VIN8

Controller and power

FET supply voltage for

LDO8.

VOUT1

LDO1 power output.

VOUT2

LDO2 power output.

VOUT3

LDO3 power output.

VOUT4

LDO4 power output.

VOUT5

LDO5 power output.

VOUT6

LDO6 power output.

VOUT7

LDO7 power output.

VOUT8

LDO8 power output.

Table 2: Pin Type Definition

Pin Type

Description

Pin Type

Description

GPI

General purpose input

GPIO

General purpose input/output

GPO

General purpose output

Chip select

DIWST

Digital Input with Schmitt trigger

DIWOSH

Digital Input without Schmitt trigger

LVDI

Low voltage digital input

ULVDI

Ultra-Low voltage digital input

SDA

Serial data

Pull-up resistor

SCL

Serial clock

Pull-down resistor

PWR

Power

GND

Ground

2.1

Input Pins

2.1.1

– Chip Select

This active-high pin is used to wake SLG51002 from a low-power reset state.

To guarantee correct operation, CS must be de-asserted whenever the voltage at the VDD pin is out of

the operating conditions boundary (that is VDD < 2.8 V, or VDD > 5.0 V).

When de-asserting the CS pin, it can have a programmable shutdown debounce time (from 0 µs to

256 µs, register CS_T_DEB).

When CS is de-asserted, all digital is forced to shut down, and any volatile memory is reset.

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