SLG51002

PMIC with High PSRR, Low Noise, Multi-Output LDOs

and Integrated Load Switches

Datasheet

Revision 3.11

25-Jul-2023

CFR0011-120-00

8 of 36

© 2023 Renesas Electronics Corporation

While CS pin is high, memory status can be checked with the MEM_STATUS bit. The MEM_STATUS bit

is reset upon any UVLO, CS de-assert, POR event, Over-temperature detection, Power Sequencer Crash

Request or Software Reset Request event, and is intended for user to write high when loading

configurations via I2C, thus allowing user to check for any event that may affect integrity of the I2C written

data.

2.1.2

SCL

– I2C Clock

The SCL signal is the I2C clock.

2.2

Bidirectional Pins

2.2.1

GPIO1 to GPIO5 and GPI6

– General Purpose Input/Output

The general-purpose input/output pins are configurable by dedicated registers (IO_GPIO<x>_CONF).

GPIO1 to GPIO5 can be configured as an input or an open-drain NMOS output. GPIO1 to GPIO4 also

can be configured as a push pull output or open-drain PMOS output. GPI6 is always an input pin.

In the LOW IQ RESET state, GPIO1 to GPIO4 are configured as input with 1MOhm pull down resistor.

GPIO5 and GPI6 are configured as inputs with no pull-up/pull-down resistor.

GPIO5 and GPI6 are low voltage pins. The user-configurable input levels for low voltage pins are 1.2 V

and 1.8 V.

GPIO1 to GPIO4 are high voltage pins and are supplied by VDDIO for input and output modes. There are

four input modes for GPIO1 to GPIO4 to get better input performance and cover voltage range from 1.2 V

to 5 V:

● Digital input without Schmitt trigger (recommended operation input voltage range - 1.5 V to VDDIO)

● Digital input with Schmitt trigger (recommended operation input voltage range - 1.5 V to VDDIO)

● Low voltage digital input (recommended operation input voltage range - 1.5 V to VDDIO)

● Ultra-Low voltage digital input (recommended operation input voltage range - 1.2 V to 1.8V)

Digital input without Schmitt trigger, Digital input with Schmitt trigger and Low voltage digital input modes

are intended for 1.5 V to VDDIO input voltage range. Ultra-Low voltage digital input mode is intended for

1.2 V to 1.8 V input voltage range, but this mode also can be used up to VDDIO voltage. The Ultra-Low

voltage digital input mode has a fixed VIH and VIL thresholds, unlike other modes, which thresholds

depends on VDDIO voltage.

2.2.2

SDA

– I2C Data

The SDA signal is the I2C data signal. It is an open-drain signal so that either side can pull it down to a

logic low level.