M65KG256AB datasheet(6/51 Pages) STMICROELECTRONICS

6 / 51 page

1 Summary description

M65KG256AB

6/51

Summary description

The M65KG256AB is a 256Mbit Double Data Rate (DDR) Low Power Synchronous DRAM

(LPSDRAM). The memory array is organized as 4 Banks of 4,194,304 Words of 16 bits each.

The device achieves low power consumption and very high-speed data transfer using the 2-bit

prefetch pipeline architecture that allows doubling the data input/output rate. Command and

address inputs are synchronized with the rising edge of the clock while data inputs/outputs are

transferred on both edges of the system clock. The M65KG256AB is well suited for handheld

battery powered applications like PDAs, 2.5 and 3G mobile phones and handheld computers.

The device architecture is illustrated in Figure 2: Functional Block Diagram. It uses Burst mode

to read and write data. It is capable of two, four, eight or sixteen-Word, sequential and

interleaved burst.

To minimize current consumption during self refresh operations, the M65KG256AB includes

three mechanisms configured via the Extended Mode Register:

●

Automatic Temperature Compensated Self Refresh (ATCSR) adapts the refresh frequency

according to the operating temperature provided by a built-in temperature sensor.

●

Partial Array Self Refresh (PASR) performs a limited refresh of a half bank, a quarter of

bank, one bank, two banks or all banks.

●

The Deep Power-Down (DPD) mode completely halts the refresh operation and achieves

minimum current consumption by cutting off the supply voltage from the whole memory

array.

The device is programmable through two registers, the Mode Register and the Extended Mode

●

The Mode Register is used to select the CAS Latency, the Burst Type (sequential,

interleaved) and the Burst Length. For more details, refer to Table 7: Mode Register

Definition, and to 3.1: Mode Register Set command (MRS) in Section 3: Commands.

●

Partial Array Self Refresh (PASR) performs a limited refresh of a half bank, a quarter of

bank, one bank, two banks or all banks.

●

The Extended Mode Register is used to configure the low-power features (PASR, ATCSR

and Driver Strength) to reduce the current consumption during the Self Refresh

operations. For more details, refer to Table 8: Extended Mode Register Definition, and to

Section 3.2: Extended Mode Register Set command (EMRS) in Section 3: Commands.

M65KG256AB Datasheet(PDF) 6 Page - STMicroelectronics