M65KG256AB datasheet(20/51 Pages) STMICROELECTRONICS

20 / 51 page

4 Operating modes

M65KG256AB

20/51

Operating modes

There are 7 operating modes that control the memory. Each of these is composed by a

sequence of commands (see Table 6: Operating Modes for a summary).

4.1

Power-Up

The DDR LPSDRAM has to be powered up and initialized in a well determined manner:

After applying power to VDD and VDDQ an initial pause of at least 200µs is required before

the signals can be toggled.

The Precharge command must then be issued to all banks. Until the command is issued

KE and UDQM/LDQM must be held High to make sure that DQ0-DQ15 remain high

impedance.

tRP after precharging all the banks, the Mode Register and the Extended Mode Register

must be set by issuing a Mode Register Set command and an Extended Mode Register

Set command, respectively. A minimum pause of tMRD must be respected after each

After the two registers are configured, two or more auto Refresh cycles must be executed

before the device is ready for normal operation.

The third and fourth steps can be swapped.

Refer to Figure 23 for a detailed description of the Power-Up AC waveforms.

4.2

Burst Read

The M65KG256AB is switched in Burst Read mode by issuing a Bank (Row) Activate command

to set the bank and column addresses to be read from, followed by a Read command (see

sections 3.3: Bank(Row) Activate command (ACT) and 3.4: Read command (READ) for

details).

Burst Read can be accompanied by an Auto Precharge cycle depending on the state of the A10

Address Input. If A10 is High (set to ‘1’) when the Burst Read command is issued, the Burst

Read operation will be followed by an Auto Precharge cycle. If A10 is Low (set to ‘0’), the row

will remain active for subsequent accesses.

Burst Read operations are performed at Word level only. Different Burst Types (sequential or

interleaved), Burst Lengths (2, 4, 8 or 16 Words) can be programmed using the Mode Register

bits. Only a CAS Latency of 3 clock cycles is available. Refer to Section 5.1: Mode Register

description, and to Section 3.1: Mode Register Set command (MRS), for details on the Mode

The Burst Read starts 3t

CK + t

AC after the Clock K rising edge where the Read command is

latched, where t

CK is the Clock period and t

AC is the access time from K or K. Data Strobe,

UDQS/LDQS, are output simultaneously with data. tRPRE prior to the first rising edge of the

data strobe, the UDQS/LDQS signals go from High-Z to Low state. This Low pulse is referred to

as the Read Preamble. The burst data are then output synchronized with the rising and falling

edge of the data strobe. UDQS/LDQS become High-Z on the next clock cycle after the Burst

M65KG256AB Datasheet(PDF) 20 Page - STMicroelectronics

M65KG256AB Datasheet(HTML) 20 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datasheet Download

Link URL