Clock line should be short

and cross no other lines.

Single Ground entry for all

Reference

Components

All Analog Components

mounted over

Analog

area of Ground

Plane

Xfmr/Amplifier

Components

mounted over

Digital area of

Digital power line should be routed

away from analog power trace.

COMMON

GROUND

PLANE

Ground entry points

close to ground pins.

Analog power line should be routed

away from Digital power trace.

Driving

source

located close

to converter.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

V

D

DB3

DB2

DB1

DB0

OEB

DR GND

DA9

DA8

DA7

DA6

V

D

DA4

DA5

VIN B-

VIN B+

AGND

V

RMB

V

RPB

V

RNB

V

REF

AGND

V

A

AGND

INT/EXT REF

V

RNA

V

RPA

V

RMA

VIN A+

VIN A-

ADC10DL065

All Digital

Ground

Plane

4 x 100:

6 x 100:

OSC

LATCH

LATCH

ABb

NC

ADC10DL065

SNAS314B – JUNE 2006 – REVISED APRIL 2013

www.ti.com

Figure 39. Example of a Suitable Layout

DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate

the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 40. The gates used in

the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be

prevented.

Best performance will be obtained with a differential input drive, compared with a single-ended drive, as

discussed in Single-Ended Operation and Driving the Analog Inputs.

As mentioned in LAYOUT AND GROUNDING, it is good practice to keep the ADC clock line as short as possible

and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can

lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90°

crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line.

Figure 40. Isolating the ADC Clock from other Circuitry with a Clock Tree

28

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