DIX4192IPFB datasheet(23/71 Pages) TI2

23 / 71 page

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DIX4192

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SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

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9.4 Device Functional Modes

9.4.1 Host Interface Operation: Serial Peripheral Interface (SPI) Mode

The DIX4192 supports a 4-wire SPI port when the CPM input (pin 18) is forced low or tied to ground. The SPI

port supports high-speed serial data transfers up to 40 Mbps. Register and data buffer write and read operations

are supported.

The CS input (pin 19) serves as the active low chip select for the SPI port. The CS input must be forced low in

order to write or read registers and data buffers. When CS is forced high, the data at the CDIN input (pin 21) is

ignored, and the CDOUT output (pin 22) is forced to a high-impedance state. The CDIN input serves as the serial

data input for the port; the CDOUT output serves as the serial data output.

The CCLK input (pin 20) serves as the serial data clock for both the input and output data. Data is latched at the

CDIN input on the rising edge of CCLK, while data is clocked out of the CDOUT output on the falling edge of

CCLK.

Figure 19 shows the SPI port protocol. Byte 0 is referred to as the command byte, where the most significant bit

(or MSB) is the read/write bit. For the R/W bit, a 0 indicates a write operation, while a 1 indicates a read

operation. The remaining seven bits of the command byte are used for the register address targeted by the write

or read operation. Byte 1 is a don’t care byte, and may be set to all zeroes. This byte is included in order to

retain protocol compatibility with earlier Texas Instruments digital audio interface and sample rate converter

products, including the DIT4096, DIT4192, the SRC418x series devices, and the SRC419x series devices.

The SPI port supports write and read operations for multiple sequential register addresses through the

implementation of an auto-increment mode. As shown in Figure 19, the auto-increment mode is invoked by

simply holding the CS input low for multiple data bytes. The register address is automatically incremented after

each data byte transferred, starting with the address specified by the command byte.

Refer to the SPI section of the Electrical Characteristics table and Figure 2 for specifications and a timing

diagram that highlight the key parameters for SPI operation.

Figure 19. Serial Peripheral Interface (SPI) Protocol for the DIX4192

DIX4192IPFB Datasheet(PDF) 23 Page - Texas Instruments

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