DIX4192IPFB datasheet(38/71 Pages) TI2

38 / 71 page

AES3BitStream

DIRSYNC

LRCK,I SFormat(input)

LRCK,Left-orRight-

JustifiedFormats(input)

±5%

DataSliporRepeatmayoccurwhentheLRCKedgesindicatedarewithinthe 5%window.

DIX4192

SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

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Table 22. Register 14: Receiver Status Register 2 (Read-Only) Field Descriptions (continued)

Buffer transfer incomplete, or no Buffer transfer interrupt indicated

Buffer transfer completed

Figure 43. Register 15: Receiver Status Register 3 (Read-Only)

7 (MSB)

0 (LSB)

OSLIP

Note: Status bits must be unmasked in control register 0x17 in order for the status interrupts to be generated.

Table 23. Register 15: Receiver Status Register 3 (Read-Only) Field Descriptions

OSLIP

Receiver Output Data Slip Error Status

OSLIP

Receiver OSLIP Error Status

No error

DIR output data Slip or Repeat error detected

An OSLIP interrupt is possible when the DIR output is used as the source for either the Port A or Port B audio serial port and the port is configured to operate in

slave mode. Figure 44 shows the timing associated with the OSLIP interrupt.

When only one audio serial port (Port A or Port B) is sourced by the DIR output, then the OSLIP status bit and interrupt applies to that port. If both Port A and

Port B are sourced by the DIR output, then the OSLIP status bit and interrupt applies to Port A only.

Figure 44. DIR Output Slip and Repeat (OSLIP) Behavior

DIX4192IPFB Datasheet(PDF) 38 Page - Texas Instruments

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