DIX4192IPFB datasheet(30/71 Pages) TI2

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DIX4192

SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

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Table 7. Register 04: Port A Control Register 2 Field Descriptions (continued)

RXCKO

Reserved

Figure 27. Register 05: Port B Control Register 1

7 (MSB)

0 (LSB)

BMUTE

BOUTS1

BOUTS0

BM/S

BFMT2

BFMT1

BFMT0

Table 8. Register 05: Port B Control Register 1 Field Descriptions

BFMT[2:0]

Port B Audio Data Format

These bits are used to set the audio input and output data format for Port B. Refer to Audio Serial Port Operation for illustrations of the

supported data formats. Refer to the Audio Serial Ports section of the Electrical Characteristics table and Figure 1 for an applicable timing

diagram and parameters.

BFMT2

BFMT1

BFMT0

Audio Data Format

24-Bit Left-Justified (default)

24-Bit Philips I2S

Unused

16-Bit Right-Justified

18-Bit Right-Justified

20-Bit Right-Justified

24-Bit Right-Justified

BM/S

Port B Slave and Master Mode

This bit is used to set the audio clock mode for Port B to either Slave or Master.

BM/S

Slave and Master Mode

Slave mode; the LRCK and BCK clocks are generated by an external source. (default)

Master mode; the LRCK and BCK clocks are derived from the Port A master clock source.

BOUTS[1:0]

Port B Output Source

These bits are used to select the output data source for Port B. The data is output at SDOUTB (pin 45).

BOUTS1

BOUTS0

Output Data Source

Port B input, for data loop back. (default)

Port A input

DIR

Reserved

BMUTE

Port B Output Mute

This bit is used to mute the Port B audio data output.

BMUTE

Output Mute

Disabled; SDOUTB is driven by the output data source. (default)

Enabled; SDOUTB is forced low.

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