DIX4192IPFB datasheet(41/71 Pages) TI2

41 / 71 page

DIX4192

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SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

Product Folder Links: DIX4192

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Figure 48. Register 19: Receiver Interrupt Mode Register 2

7 (MSB)

0 (LSB)

CSCRCM1

CSCRCM0

PARITYM1

PARITYM0

VBITM1

VBITM0

BPERRM1

BPERRM0

Table 27. Register 19: Receiver Interrupt Mode Register 2 Field Descriptions

CSCRCM[1:0]

Channel Status CRC Error Interrupt Mode

CSCRCM1

CSCRCM0

Interrupt Active State

Rising edge active (default)

Falling edge active

Level active

Reserved

PARITYM[1:0]

Parity Error Interrupt Mode

PARITYM1

PARITYM0

Interrupt Active State

Rising edge active (default)

Falling edge active

Level active

Reserved

VBITM[1:0]

Validity Error Interrupt Mode

VBITM1

VBITM0

Interrupt Active State

Rising edge active (default)

Falling edge active

Level active

Reserved

BPERRM[1:0]

Biphase Encoding Error Interrupt Mode

BPERRM1

BPERRM0

Interrupt Active State

Rising edge active (default)

Falling edge active

Level active

Reserved

Figure 49. Register 1A: Receiver Interrupt Mode Register 3

7 (MSB)

0 (LSB)

OSLIPM1

OSLIPM0

Table 28. Register 1A: Receiver Interrupt Mode Register 3 Field Descriptions

OSLIPM[1:0]

Receiver Output Data Slip Error Interrupt Mode

OSLIPM1

OSLIPM0

Interrupt Active State

Rising edge active (default)

Falling edge active

Level active

Reserved

DIX4192IPFB Datasheet(PDF) 41 Page - Texas Instruments

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