STM32L4S5AI datasheet(50/275 Pages) STMICROELECTRONICS

50 / 275 page

Functional overview

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

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DocID030322 Rev 2

3.30

Advanced encryption standard hardware accelerator (AES)

The STM32L4Sxxx devices embed an AES hardware accelerator that can be used both to

encipher and to decipher data using an AES algorithm.

The AES peripheral supports:

•

Encryption/decryption using AES Rijndael block cipher algorithm

•

NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm

•

128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x

32-bit registers)

•

Electronic codebook (ECB), cipher block chaining (CBC), Counter mode (CTR), Galois

Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher

Message Authentication Code mode (CMAC) supported

•

Key scheduler

•

Key derivation for decryption

•

128-bit data block processing

•

128-bit, 256-bit key length

•

1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer

•

One 128-bit Register for the initialization vector when AES is configured in CBC mode

or for the 32-bit counter initialization when CTR mode is selected, GCM mode or

CMAC mode

•

Automatic data flow control with support of direct memory access (DMA) using 2

channels, one for incoming data, and one for outcoming data

•

Suspend a message if another message with a higher priority needs to be processed.

3.31

HASH hardware accelerator (HASH)

The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-

1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the

HMAC (keyed-hash message authentication code) algorithm suitable for a variety of

applications.

It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256

algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for

messages of up to (264 - 1) bits, while the HMAC algorithms provide a way of authenticating

messages by means of hash functions. The HMAC algorithms consist in calling the SHA-1,

SHA-224, SHA-256 or MD5 hash function twice.

3.32

Timers and watchdogs

The STM32L4Sxxx devices include two advanced control timers, up to nine general-

purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick

timer.

The Table 10 below compares the features of the advanced control, general-purpose and

basic timers.

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