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STM32L4S5AI Datasheet(PDF) 93 Page - STMicroelectronics |
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STM32L4S5AI Datasheet(HTML) 93 Page - STMicroelectronics |
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93 / 275 page  DocID030322 Rev 2 93/275 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description 116 98 A2 142 A11 B4 - 142 C4 A11 B4 PE1 I/O FT - DCMI_D3, LCD_VSYNC, FMC_NBL1, TIM17_CH1, EVENTOUT - 99 D3 143 A12 B3 99 143 A1 A12 B3 VSS S - - - - 100 C4 144 B12 A3 10 0 144 B2 B12 A3 VDD S - - - - - - - - A2 - - - - A2 PH2 I/O FT - OCTOSPIM_P1_IO4 , EVENTOUT - - - - - B2 - - - - B2 PI7 I/O FT - TIM8_CH3, DCMI_D7, EVENTOUT - - - - - B1 - - - - B1 PI9 I/O FT - OCTOSPIM_P2_IO2 , CAN1_RX, EVENTOUT - - - - - A1 - - - - A1 PI10 I/O FT - OCTOSPIM_P2_IO1 , EVENTOUT - 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF - These GPIOs must not be used as current sources (for example to drive a LED). 2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0432 reference manual. 3. NC (not-connected) balls must be left unconnected. However, PF8 and PF9 NC' IOs are not bonded. They must be configured by software to output push-pull and forced to 0 in the output data register to avoid extra current consumption in low-power modes. 4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated. Table 15. STM32L4Sxxx pin definitions (continued) Pin Number Pin name (functio n after reset) Alternate functions Additional functions STM32L4S5xx STM32L4S7xx STM32L4S9xx |
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