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STM32L4S5AI Datasheet(PDF) 55 Page - STMicroelectronics

Part # STM32L4S5AI
Description  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 150DMIPS, up to 2MB Flash, 640KB SRAM, LCD-TFT & MIPI DSI, AESHASH
PDF  275 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L4S5AI Datasheet(HTML) 55 Page - STMicroelectronics

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STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
Functional overview
63
The I2C peripheral supports:
•
I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and master modes, multimaster capability
–
Standard-mode (Sm), with a bitrate up to 100 kbit/s
–
Fast-mode (Fm), with a bitrate up to 400 kbit/s
–
Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
•
System management bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with ACK
control
–
Address resolution protocol (ARP) support
–
SMBus alert
•
Power system management protocol (PMBusTM) specification rev 1.1 compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 5: Clock tree
•
Wakeup from Stop mode on address match
•
Programmable analog and digital noise filters
•
1-byte buffer with DMA capability
Table 11. I2C implementation
I2C features(1)
1. X: supported
I2C1
I2C2
I2C3
I2C4
Standard-mode (up to 100 kbit/s)
X
X
X
X
Fast-mode (up to 400 kbit/s)
X
X
X
X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
X
X
X
X
Programmable analog and digital noise filters
X
X
X
X
SMBus/PMBus hardware support
X
X
X
X
Independent clock
X
X
X
X
Wakeup from Stop 0, Stop 1 mode on address match
X
X
X
X
Wakeup from Stop 2 mode on address match
-
-
X
-



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