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STM32L4S5AI Datasheet(PDF) 27 Page - STMicroelectronics |
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STM32L4S5AI Datasheet(HTML) 27 Page - STMicroelectronics |
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27 / 275 page ![]() Stop 1 LPR No Off ON LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DACx (x=1,2) OPAMPx (x=1,2) USARTx (x=1...5)(5) LPUART1(5) I2Cx (x=1...4)(6) LPTIMx (x=1,2) *** All other peripherals are frozen Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...5)(5) LPUART1(5) I2Cx (x=1...4)(6) LPTIMx (x=1,2) OTG_FS(7) Stop 2 LPR No Off ON LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) I2C3(6) LPUART1(5) LPTIM1 *** All other peripherals are frozen Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) I2C3(6) LPUART1(5) LPTIM1 Standby LPR Powered Off Off SRAM2 ON LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off *** I/O configuration can be floating, pull- up or pull-down Reset pin 5 I/Os (WKUPx)(8) BOR, RTC, IWDG OFF Powered Off Shutdown OFF Powered Off Off Powered Off LSE RTC *** All other peripherals are powered off *** I/O configuration can be floating, pull- up or pull-down(9) Reset pin 5 I/Os (WKUPx)(8) RTC Table 4. STM32L4S5xx modes overview (continued) Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source |
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