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STM32L4S5AI Datasheet(PDF) 28 Page - STMicroelectronics |
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STM32L4S5AI Datasheet(HTML) 28 Page - STMicroelectronics |
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28 / 275 page  1. LPR means Main regulator is OFF and Low-power regulator is ON. 2. All peripherals can be active or clock gated to save power consumption. 3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. 4. The SRAM1, SRAM2 and SRAM3 clocks can be gated on or off independently. 5. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 6. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 7. OTG_FS wakeup by resume from suspend and attach detection protocol event. 8. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 9. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. |
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