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STM32L4S5AI Datasheet(PDF) 62 Page - STMicroelectronics |
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STM32L4S5AI Datasheet(HTML) 62 Page - STMicroelectronics |
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62 / 275 page ![]() Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 62/275 DocID030322 Rev 2 • Each of the five following phases can be configured independently (enable, length, single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase • HyperbusTM support • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Timeout management • Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error 3.45 OctoSPI IO manager (OctoSPIIOM) The OctoSPI IO Manager is a low level interface allowing: • Efficient OctoSPI pin assignment with a full IO Matrix (before alternate function map) • Multiplexing single/dual/quad/octal SPI interface over the same bus The OctoSPI IO Manager has the following features: • Support up to two single/dual/quad/octal SPI Interface • Support up to eight ports for pin assignment • Fully programmable IO matrix for pin assignment by function (data/control/clock) • Muxer for Single/Dual/Quad/Octal SPI interface multiplexing over the same bus 3.46 Development support 3.46.1 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using two pins only instead of five required by the JTAG (JTAG pins could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. |
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