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STM32L4S5AI Datasheet(PDF) 180 Page - STMicroelectronics |
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STM32L4S5AI Datasheet(HTML) 180 Page - STMicroelectronics |
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180 / 275 page ![]() Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx 180/275 DocID030322 Rev 2 All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 32 for standard I/Os, and in Figure 32 for 5 V tolerant I/Os. Figure 32. I/O input characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed VOL/VOH). 1. Refer to Figure 32: I/O input characteristics. 2. Tested in production. 3. Guaranteed by design. 4. Max(VDDXXX) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table. 5. All TX_xx IO except FT_lu, FT_u, PB2 and PC3. 6. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula: ITotal_Ileak_max = 10 µA + [number of IOs where VIN is applied on the pad] ₓ Ilkg(Max). 7. To sustain a voltage higher than MIN(VDD, VDDA, VDDUSB, VLCD) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled. 8. Refer to Ibias in Table 83: OPAMP characteristics for the values of the OPAMP dedicated input leakage current. 9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). MSv37613V1 Teste d in production CMOS requirement Vih min = 0 .7xV DDIO x Based on simulati on Vi h min = 0. 61xV DDIOx +0.05 for 1.08<V DDIOx <1.62 or 0.49xV DDIOx +0.2 6 for VDDI Ox>1 .62 Based on simu lation Vil m ax =0.43xV DDIOx -0.1 for 1.08 <VDDIOx <1.62 or 0.39xV DDIOx -0.06 for VDDIO x>1.62 Tested in produ ction CMOS requirement Vil ma x = 0.3xVdd TTL requirement Vih min = 2V TTL requirement Vil max = 0.8V |
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