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STM32L4S5AI Datasheet(PDF) 231 Page - STMicroelectronics

Part # STM32L4S5AI
Description  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 150DMIPS, up to 2MB Flash, 640KB SRAM, LCD-TFT & MIPI DSI, AESHASH
PDF  275 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L4S5AI Datasheet(HTML) 231 Page - STMicroelectronics

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STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
Electrical characteristics
250
Synchronous waveforms and timings
Figure 48 through Figure 51 represent synchronous waveforms and Table 105
through Table 108 provide the corresponding timings. The results shown in these
tables are obtained with the following FMC configuration:
•
BurstAccessMode = FMC_BurstAccessMode_Enable
•
MemoryType = FMC_MemoryType_CRAM
•
WriteBurst = FMC_WriteBurst_Enable
•
CLKDivision = 1
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the THCLK is the HCLK clock period.
•
For 2.7 V ≤ VDD ≤ 3.6 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and 54 MHz
for CLKDIV = 0x0 at CL = 30 pF (on FMC_CLK).
•
For 1.71 V ≤ VDD ≤ 2.7 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and
32 MHz for CLKDIV = 0x0 at CL= 20 pF (on FMC_CLK).
1. CL = 30 pF.
2. Guaranteed by characterization results.
Table 104. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
10THCLK-0.5
10THCLK+1
ns
tw(NWE)
FMC_NWE low time
7THCLK-0.5
7THCLK+0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
7THCLK+12.5
-
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid
5THCLK+13
-



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