ADC32RF44IRMPR datasheet(54/135 Pages) TI2

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ADC32RF44

SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017

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9.4.2.5 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output

Table 18 lists the available JESD204B formats and valid ranges for the ADC32RF44 with decimation (single-

band DDC) when using real output format. The ranges are limited by the SerDes line rate and the maximum

ADC sample frequency. The sample alignment on the different lanes is shown in Table 19.

Table 18. JESD Mode Options: Single-Band Real Output (Wide Bandwidth)

DECIMATION

SETTING

(Complex)

NUMBER OF

ACTIVE DDCS

PLL

MODE

JESD

MODE0

JESD

MODE1

JESD

MODE2

RATIO

[fSerDes / fCLK

(Gbps / GSPS)]

Divide-by-4

(Divide-by-2 real)

1 per channel

20X

2.5

40X

Divide-by-6

(Divide-by-3 real)

1 per channel

20X

1.67

40X

3.33

40X

(1)

Blue shading indicates channel A and yellow shading indicates channel B.

Table 19. JESD Sample Lane Alignment: Single-Band Real Output (Wide Bandwidth)(1)

OUTPUT

LANE

LMFS = 8224

LMFS = 4244

LMFS = 4211

DA0

A0[15:8]

A0[7:0]

DA1

A1[15:8]

A1[7:0]

A0[15:8]

A0[7:0]

A1[15:8]

A1[7:0]

A0[15:8]

DA2

A2[15:8]

A2[7:0]

A2[15:8]

A2[7:0]

A3[15:8]

A3[7:0]

A0[7:0]

DA3

A3[15:8]

A3[7:0]

DB0

B0[15:8]

B0[7:0]

DB1

B1[15:8]

B1[7:0]

B0[15:8]

B0[7:0]

B1[15:8]

B1[7:0]

B0[15:8]

DB2

B2[15:8]

B2[7:0]

B0[15:8]

B2[7:0]

B3[15:8]

B3[7:0]

B0[7:0]

DB3

B3[15:8]

B3[7:0]

ADC32RF44IRMPR Datasheet(PDF) 54 Page - Texas Instruments

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