CLKIN

DOUT

Bitream not valid

(analog settling)

tISTART

DVDD

...

Valid bitstream

AVDD

Test Pattern

tASTART

CLKIN

DOUT

t

CLKIN

t

HIGH

t

LOW

t

D

t

H

t

r / tf

12

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

SBAS734C – MARCH 2017 – REVISED JANAURY 2020

www.ti.com

Product Folder Links: AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25

Submit Documentation Feedback

Copyright © 2017–2020, Texas Instruments Incorporated

(1)

The output of the Manchester encoded versions of the AMC1306Ex can change with every edge of CLKIN with a typical delay of 6 ns;

see the Manchester Coding Feature section for additional details.

7.11 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fCLKIN

CLKIN clock frequency

4.5 V

≤ AVDD ≤ 5.5 V

5

21

MHz

3.0 V

≤ AVDD ≤ 5.5 V

5

20

tCLKIN

CLKIN clock period

4.5 V

≤ AVDD ≤ 5.5 V

47.6

200

ns

3.0 V

≤ AVDD ≤ 5.5 V

50

200

tHIGH

CLKIN clock high time

20

25

120

ns

tLOW

CLKIN clock low time

20

25

120

ns

tH

DOUT hold time after rising edge

of CLKIN

AMC1306Mx(1),

CLOAD = 15 pF

3.5

ns

tD

Rising edge of CLKIN to DOUT

valid delay

AMC1306Mx(1), CLOAD = 15 pF

15

ns

tr

DOUT rise time

10% to 90%, 2.7 V

≤ DVDD ≤ 3.6 V,

CLOAD = 15 pF

0.8

3.5

ns

10% to 90%, 4.5 V

≤ DVDD ≤ 5.5 V,

CLOAD = 15 pF

1.8

3.9

tf

DOUT fall time

90% to 10%, 2.7 V

≤ DVDD ≤ 3.6 V,

CLOAD = 15 pF

0.8

3.5

ns

90% to 10%, 4.5 V

≤ DVDD ≤ 5.5 V,

CLOAD = 15 pF

1.8

3.9

tISTART

Interface startup time

DVDD at 2.7 V (min) to DOUT valid with

AVDD

≥ 3.0 V

32

32

CLKIN

cycles

tASTART

Analog startup time

AVDD step to 3.0 V with DVDD

≥ 2.7 V,

0.1% settling

0.5

ms

Figure 1. Digital Interface Timing

Figure 2. Device Startup Timing