DAC7750IPWPR.B datasheet(23/56 Pages) TI2

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8.3.8 Watchdog Timer

This feature is useful to make sure that communication between the host processor and the DACx750 has not

been lost. The feature can be enabled by setting the WDEN bit of the Configuration Register to 1. The watchdog

timeout period can be set using the WDPD bits of the configuration register, as shown in Table 8-1. The timer

period is based off an internal oscillator with a typical value of 8 MHz.

Table 8-1. Watchdog Timeout Period

WDPD BITS

WATCHDOG TIMEOUT PERIOD (Typical)

10 ms

51 ms

102 ms

204 ms

If the watchdog timer is enabled, these devices must have an SPI frame with 0x95 as the write address byte

written to the device within the programmed timeout period. Otherwise, the ALARM pin asserts low and the

WD-FLT bit of the status register is set to 1. The ALARM pin can be asserted low for any of the different

conditions explained in Section 8.3.7. To reset the WD-FLT bit to 0, use a software reset, disable the watchdog

timer, or power down the device.

8.3.9 Frame Error Checking

In noisy environments, error checking can be used to check the integrity of SPI data communication between

the DACx750 and the host processor. To enable this feature, set the CRCEN bit of the Configuration Register

to 1. The frame error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is,

100000111). When error checking is enabled, the SPI frame width is 32 bits, as shown in Table 8-2. Start with

the default 24-bit frame, enable frame error checking, and then switch to the 32-bit frame. The normal 24-bit

SPI data are appended with an 8-bit CRC polynomial by the host processor before feeding to the device. For a

Table 8-2. SPI Frame with Frame Error Checking

Enabled

BIT 31:BIT 8

BIT 7:BIT 0

Normal SPI frame data

8-bit CRC polynomial

When in CRC mode, the DACx750 calculates CRC words every 32 clocks, unconditional of when the LATCH

pin toggles. The DACx750 decodes the 32-bit input frame data to compute the CRC remainder. If no error

exists in the frame, the CRC remainder is zero. When the remainder is non-zero (that is, the input frame has

single- or multiple-bit errors), the ALARM pin asserts low and the CRC-FLT bit of the status register is set to

1. The ALARM pin can be asserted low for any of the different conditions explained in Section 8.3.7. To reset

the CRC-FLT bit to 0, either issue software reset command of 0x96, disable the frame error checking, or power

down the device. In the case of a CRC error, the specific SPI frame is blocked from writing to the device.

If CRC mode is enabled on the first frame issued to the device after power up, issue a no operation, or NOOP,

command to the device in order to reset the SPI clock and SPI frame alignment in the event that any transients

on the SCLK line are interpreted as SCLK periods. A NOOP command can be issued to the device by simply

toggling the LATCH pin without any SCLK periods.

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DAC7750, DAC8750

SBAS538D – DECEMBER 2013 – REVISED DECEMBER 2021

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