DAC7750IPWPR.B datasheet(34/56 Pages) TI2

34 / 56 page

8.6.1.5 Status Register

This read-only register consists of four ALARM status bits (CRC-FLT, WD-FLT, I-FLT, and T-FLT) and the SR-ON

bit that shows the slew rate status, as shown in Table 8-18.

Table 8-18. Status Register

DATA BIT(S)

NAME

DEFAULT

DESCRIPTION

DB15:DB5

Reserved

000 0000 0000

Reserved. Reading these bits returns 0.

DB4

CRC-FLT

Bit = 1 indicates CRC error on SPI frame.

Bit = 0 indicates normal operation.

DB3

WD-FLT

Bit = 1 indicates watchdog timer timeout.

Bit = 0 indicates normal operation.

DB2

I-FLT

Bit = 1 indicates an open circuit or a compliance voltage violation in IOUT

Bit = 0 indicates IOUT load is at normal condition.

DB1

SR-ON

Bit = 1 when DAC code is slewing as determined by SRCLK and SRSTEP.

Bit = 0 when DAC code is not slewing.

DB0

T-FLT

Bit = 1 indicates die temperature is over 142°C.

Bit = 0 indicates die temperature is not over 142°C.

These devices continuously monitor the current output and die temperature. When an alarm occurs, the

corresponding ALARM status bit is set (1). Whenever an ALARM status bit is set, it remains set until the event

that caused it is resolved. The ALARM bit can only be cleared by performing a software reset, a power-on reset

(by cycling power), or by having the error condition resolved. These bits are reasserted if the alarm condition

continues to exist in the next monitoring cycle.

The ALARM bit goes to 0 when the error condition is resolved.

DAC7750, DAC8750

SBAS538D – DECEMBER 2013 – REVISED DECEMBER 2021

www.ti.com

Submit Document Feedback

Product Folder Links: DAC7750 DAC8750

DAC7750IPWPR.B Datasheet(PDF) 34 Page - Texas Instruments

DAC7750IPWPR.B Datasheet(HTML) 34 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL