DAC7750IPWPR.B datasheet(32/56 Pages) TI2

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8.6 Register Maps

Table 8-11 shows the available registers on the DACx750 devices. See Section 8.6.1 for descriptions of all

DACx750 registers.

Table 8-11. Command and Register Map

COMMAND

READ AND

WRITE

ACCESS

DATA BITS (DB15:DB0)

15:14

10:9

Control

REXT

OUTEN

SRCLK

SRSTEP

SREN

Reserved

RANGE

Configuration

X(1)

CALEN

HARTEN

CRCEN

WDEN

WDPD

DAC Data(2)

D15:D0

No operation(3)

—

Read Operation (3)

—

READ ADDRESS

Reset

RESET

Status

Reserved

CRC-FLT

WD-FLT

I-FLT

SR-ON

T-FLT

DAC Gain Calibration

(2)

G15:G0, unsigned

DAC Zero Calibration

(2)

Z15:Z0, signed

Watchdog Timer

Reset (3)

—

CRC Fault Reset (3)

—

(1)

X denotes don't care bits.

(2)

DAC8750 (16-bit version) shown. DAC7750 (12-bit version) contents are located in DB15:DB4.

For DAC7750, DB3:DB0 are don't care bits when writing and zeros when reading.

(3)

No operation, read operation, watchdog timer reset, and CRC fault reset are commands and not registers.

8.6.1 DACx750 Register Descriptions

8.6.1.1 Control Register

The DACx750 control register is written to at address 0x55. Table 8-12 shows the description for the control

Table 8-12. Control Register

DATA BIT(S)

NAME

DEFAULT

DESCRIPTION

DB15:DB14

Reserved

Reserved. Do not write any value other than zero to these bits.

DB13

REXT

External current setting resistor enable.

DB12

OUTEN

Output enable.

Bit = 1: Output is determined by RANGE bits.

Bit = 0: Output is disabled. IOUT is Hi-Z.

DB11:DB8

SRCLK[3:0]

0000

Slew rate clock control. Ignored when bit SREN = 0.

DB7:DB5

SRSTEP[2:0]

000

Slew rate step size control. Ignored when bit SREN = 0.

DB4

SREN

Slew Rate Enable.

Bit = 1: Slew rate control is enabled, and the ramp speed of the output change is determined

by SRCLK and SRSTEP.

Bit = 0: Slew rate control is disabled. Bits SRCLK and SRSTEP are ignored. The output

changes to the new level immediately.

DB3

Reserved

Reserved. Must be set to 0.

DB2:DB0

RANGE[2:0]

000

Output range bits.

DAC7750, DAC8750

SBAS538D – DECEMBER 2013 – REVISED DECEMBER 2021

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