DAC7750IPWPR.B datasheet(33/56 Pages) TI2

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8.6.1.2 Configuration Register

The DACx750 configuration register is written to at address 0x57. Table 8-13 summarizes the description for the

configuration register bits.

Table 8-13. Configuration Register

DATA BIT(S)

NAME

DEFAULT

DESCRIPTION

DB15:DB6

Reserved

00 0000 0000

Reserved. Do not write any value other than zero to these bits.

DB5

CALEN

User calibration enable. When user calibration is enabled, the DAC data are

adjusted according to the contents of the gain and zero calibration registers. See

the Section 8.3.10 section.

DB4

HARTEN

Enable interface through HART-IN pin (only valid for IOUT set to 4-mA to 20-mA

range through RANGE bits).

Bit = 1: HART signal is connected through internal resistor and modulates output

current.

Bit = 0: HART interface is disabled.

DB3

CRCEN

Enable frame error checking.

DB2

WDEN

Watchdog timer enable.

DB1:DB0

WDPD[1:0]

Watchdog timeout period.

8.6.1.3 DAC Registers

The DAC registers consist of a DAC data register (Table 8-14), a DAC gain calibration register (Table 8-15),

and a DAC zero calibration register (Table 8-16). User calibration as described in Section 8.3.10 is a feature

that allows for trimming the system gain and zero errors. Table 8-14 through Table 8-16 show the DAC8750,

16-bit version of these registers. The DAC7750 (12-bit version) register contents are located in DB15:DB4. For

DAC7750, DB3:DB0 are don't care bits when writing and zeros when reading.

Table 8-14. DAC Data Register

DATA BITS

NAME

DEFAULT

DESCRIPTION

DB15:DB0

D15:D0

0x0000

DAC data register. Format is unsigned straight binary.

Table 8-15. DAC Gain Calibration Register

DATA BITS

NAME

DEFAULT

DESCRIPTION

DB15:DB0

G15:G0

0x0000

Gain calibration register for user calibration. Format is unsigned straight binary.

Table 8-16. DAC Zero Calibration Register

DATA BITS

NAME

DEFAULT

DESCRIPTION

DB15:DB0

Z15:Z0

0x0000

Zero calibration register for user calibration. Format is twos complement.

8.6.1.4 Reset Register

The DACx750 reset register is written to at address 0x56. Table 8-17 provides the description.

Table 8-17. Reset Register

DATA BIT(S)

NAME

DEFAULT

DESCRIPTION

DB15:DB1

Reserved

000 0000 0000 0000

Reserved. Writing to these bits does not cause any change.

DB0

RESET

Software reset bit. Writing 1 to the bit performs a software reset that resets all

registers and the ALARM status to the respective power-on reset default value.

After reset completes, the RESET bit clears itself.

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DAC7750, DAC8750

SBAS538D – DECEMBER 2013 – REVISED DECEMBER 2021

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