L9679ETR datasheet(73/127 Pages) STMICROELECTRONICS

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The above diagnostic results are processed through a 10-bit analog-to-digital algorithmic converter. These tests

can be addressed in two different ways, with a high-level approach or a low-level one. The main difference

between the two approaches is that with the low-level approach the user is allowed to precisely control the

diagnostic circuitry, also deciding the proper timings involved in the different tests. On the other hand, the high-

level approach is an automatic way of getting diagnostic results for which an internal state machine is taking care

of instructions and timings (reduced number of SPI frames required to run the diagnostic).

The following figure shows the block diagram of the squib/pyroswitch diagnostics.

Figure 15. Deployment loop diagnostics

SSxy

SFx

SRx

SGx

22nF

1nF

22nF

Ilimit =70 mA

8/40 mA

Gain = 5.25

Voffset

A to D

10bit

Tot err = ±4LSB

LSB = 2.5/1024 V

HV analog MUX

Vref =2v5

Short to GND

Rleak >10 kΩ no detection

Rleak <1 kΩ detection

Rleak >10 kΩ no detection

Rleak <1 kΩ detection

Short to BAT

Squib/Pyroswitch resistor LOW

Squib/Pyroswitch resistor HIGH

VRCM (voltage regulator current monitor)

Squib/Pyroswitch resistance measure

(system error < 8%)

Rsquib/

pyroswitch

1Ω to 10Ω

Vout

Vgnd or

VBat

RLeak

EMI low pass

filter

Squib/Pyroswitch

loop driver and

diagnostic

blocks

3v3 supply

VSYNC

ISRC

VER pin

(from Energy Reserve)

Safing

transistor

VSAT

Vgnd or

VBat

Bypass

ISINK

Ipulldown

I=1mA

GNDA

ISRC_CURR_SEL

GADG0903181202PS

The leakage diagnostic includes short-to-battery, short-to-ground and shorts between loops. The test is applied to

each SFx and SRx pin so shorts can be detected regardless of the resistance between the squib/pyroswitch pins.

7.4.1

Low-level diagnostic approach

In this approach, each of the test steps described in the sections below requires user intervention by issuing the

proper SPI command.

High-voltage leakage test for oxide isolation check

This test is mandatory to address possible leakages that could not be experienced at low voltages on SFx or SRx

pins. The Isource current generator (ISRC) is enabled on the chosen SFx pin. To confirm that the SFx pin has then

reached a suitable voltage level, a dedicated ADC measurement on the SFx pin can be requested. Once this test

is performed, a leakage test on SFx and SRx pins can be issued to double check possible leakages.

Leakage-to-battery/Ground diagnostics

Prior to the real test, the voltage regulator current monitor block (VRCM) has to be tested and validated. The

validation of VRCM goes into verifying both the short-to-battery and short-to-ground flags.

L9679E

Deployment drivers

DS12485 - Rev 8

page 73/127

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