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DP83849IFVS/NOPB Datasheet(PDF) 38 Page - Texas Instruments |
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DP83849IFVS/NOPB Datasheet(HTML) 38 Page - Texas Instruments |
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38 / 108 page ![]() DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs, the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit. For transmit VOD testing, the Packet BIST Continuous Mode can be used to allow continuous data transmission, setting BIST_CONT_MODE, bit 5, of CDCTRL1 (1Bh). The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 (1Bh), bits [15:8]. 38 Configuration Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849IF |
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