DP83849IFVSSLASHNOPB datasheet(42/108 Pages) TI2

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Channel A

Channel B

MII

Port

MII

Port

10BASE-T

10BASE-TX

100BASE-FX

10BASE-T

10BASE-TX

100BASE-FX

DP83849IF

SNOSAX8D – JUNE 2009 – REVISED APRIL 2013

www.ti.com

Table 6-2. Supported SCMII Packet Sizes at +/-50ppm Frequency Accuracy

Latency Tolerance

Recommended Packet Size at +/- 50ppm

Start Threshold RBR[1:0]

100Mb

10Mb

100Mb

10Mb

01 (default)

4 bits

8 bits

4,000 bytes

9,600 bytes

4 bits

8 bits

4,000 bytes

9,600 bytes

12 bits

8 bits

9,600 bytes

12 bits

8 bits

9,600 bytes

6.5

FLEXIBLE MII PORT ASSIGNMENT

The DP83849IF supports a flexible assignment scheme for each of the channels to the MII/RMII interface.

Either of the MII ports may be assigned to the internal channels A/B. These values are controlled by the

RMII and Bypass Register (RBR), address 17h. Transmit assignments and Receive assignments can be

made separately to allow even more flexibility (i.e. both channels could transmit from MII A while still

allowing separate receive paths for the channels).

In addition, the opposite receive channel may be used as the transmit source for each channel. As shown

in Figure 6-1, Channel A receive data may be used as the Channel B transmit data source while Channel

B receive data may be used as the Channel A transmit data source. For proper clock synchronization, this

function requires the device be in RMII mode or Single Clock MII mode of operation. A configuration strap

is provided on pin 56, RXD2_B/EXTENDER_EN to enable this mode.

Figure 6-1. MII Port Mapping

6.5.1

RX MII Port Mapping

Note that Channel A is the master of MII Port A, and Channel B is the master of MII Port B. This means

that in order for Channel B to control MII Port A, Channel A must be configured to either control MII Port B

or be Disabled; the reverse is also true.

RX MII Port Mapping controls and configurations are shown in the following tables:

MAC Interface

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