DP83849IFVSSLASHNOPB datasheet(88/108 Pages) TI2

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DP83849IF

SNOSAX8D – JUNE 2009 – REVISED APRIL 2013

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10.2.6

PHY Control Register (PHYCR)

This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address.

It also provides Pause Negotiation status.

Table 10-21. PHY Control Register (PHYCR), address 19h

Bit

Bit Name

Default

Description

MDIX_EN

Strap, RW

Auto-MDIX Enable:

1 = Enable Auto-neg Auto-MDIX capability.

0 = Disable Auto-neg Auto-MDIX capability.

The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the BMCR

as well.

FORCE_MDIX

0, RW

Force MDIX:

1 = Force MDI pairs to cross.

(Receive on TPTD pair, Transmit on TPRD pair)

0 = Normal operation.

PAUSE_RX

0, RO

Pause Receive Negotiated:

Indicates that pause receive should be enabled in the MAC. Based on ANAR[11:10]

and ANLPAR[11:10] settings.

This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3,

“Pause Resolution”, only if the Auto-Negotiated Highest Common Denominator is a

full duplex technology.

PAUSE_TX

0, RO

Pause Transmit Negotiated:

Indicates that pause transmit should be enabled in the MAC. Based on ANAR[11:10]

and ANLPAR[11:10] settings.

This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3,

Pause Resolution, only if the Auto-Negotiated Highest Common Denominator is a

full duplex technology.

BIST_FE

0, RW/SC

BIST Force Error:

1 = Force BIST Error.

0 = Normal operation.

This bit forces a single error, and is self clearing.

PSR_15

0, RW

BIST Sequence select:

1 = PSR15 selected.

0 = PSR9 selected.

BIST_STATUS

0, LL/RO

BIST Test Status:

1 = BIST pass.

0 = BIST fail. Latched, cleared when BIST is stopped.

For a count number of BIST errors, see the BIST Error Count in the CDCTRL1

BIST_START

0, RW

BIST Start:

1 = BIST start.

0 = BIST stop.

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