I/O(2)

40-

Pin

PDIP

40-

Pin

UQFN

44-

Pin

QFN

44-

Pin

TQFP

A/D

Reference Comparator Timers

CCP

CWG

ZCD Interrupt EUSART

DSM

MSSP

Pull-

up

Basic

RB7

40

15

17

17

ANB7

DAC1OUT2

—

T6IN(1)

—

—

—

IOCB7

RX2/

DT2(1,3)

—

—

Y

ICSPDAT

RC0

15

30

34

32

ANC0

—

—

T1CKI(1)

T3CKI(1)

T3G(1)

—

—

—

IOCC0

—

—

—

Y

SOSCO

RC1

16

31

35

35

ANC1

—

—

—

CCP2(1)

—

—

IOCC1

—

—

—

Y

SOSCIN

SOSCI

RC2

17

32

36

36

ANC2

—

—

T5CKI(1) CCP1(1)

—

—

IOCC2

—

—

—

Y

—

RC3

18

33

37

37

ANC3

—

—

T2IN(1)

—

—

—

IOCC3

—

—

SCK1(1)

SCL1(3,4)

Y

—

RC4

23

38

42

42

ANC4

—

—

—

—

—

—

IOCC4

—

—

SDI1(1)

SDA1(3,4)

—

—

RC5

24

39

43

43

ANC5

—

—

T4IN(1)

—

—

—

IOCC5

—

—

—

Y

—

RC6

25

40

44

44

ANC6

—

—

—

—

—

—

IOCC6 CK1(1,3)

—

—

Y

—

RC7

26

1

1

1

ANC7

—

—

—

—

—

—

IOCC7

RX1/

DT1(1,3)

—

—

Y

—

RD0

19

34

38

38

AND0

—

—

—

—

—

—

—

—

—

—

Y

—

RD1

20

35

39

39

AND1

—

—

—

—

—

—

—

—

—

—

Y

—

RD2

21

36

40

40

AND2

—

—

—

—

—

—

—

—

—

—

Y

—

RD3

22

37

41

41

AND3

—

—

—

—

—

—

—

—

—

—

Y

—

RD4

27

2

2

2

AND4

—

—

—

—

—

—

—

—

—

—

Y

—

RD5

28

3

3

3

AND5

—

—

—

—

—

—

—

—

—

—

Y

—

RD6

29

4

4

4

AND6

—

—

—

—

—

—

—

—

—

—

Y

—

RD7

30

5

5

5

AND7

—

—

—

—

—

—

—

—

—

—

Y

—

RE0

8

23

25

25

ANE0

—

—

—

—

—

—

—

—

—

—

Y

—

RE1

9

24

26

26

ANE1

—

—

—

—

—

—

—

—

—

—

Y

—

RE2

10

25

27

27

ANE2

—

—

—

—

—

—

—

—

—

—

Y

—

RE3

1

16

18

18

—

—

—

—

—

—

—

IOCE3

—

—

—

Y

Vpp/

MCLR

VSS

12

6

6

6

—

—

—

—

—

—

—

—

—

—

—

—

VSS

VDD

11

7

7

7

—

—

—

—

—

—

—

—

—

—

—

—

VDD

VDD

32

26

28

28

—

—

—

—

—

—

—

—

—

—

—

—

VSS

VSS

31

27

30

29

—

—

—

—

—

—

—

—

—

—

—

—

VSS

OUT(2) —

—

—

—

ADGRDA

ADGRDB

—

C1OUT

C2OUT

TMR0

CCP1

CCP2

PWM3

PWM4

CWG1A

CWG1B

CWG1C

CWG1D

—

—

TX1/

CK1(3)

DT1(3)

TX2/

CK2(3)

DT2(3)

DSM

SDO1

SCK1

SDO2

SCK2

—

—

Note: 

1.

This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the

peripheral input selection table for details on which PORT pins may be used for this signal.

2.

All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the

peripheral output selection table.

3.

This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.

4.

These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will

operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.

PIC18F2X/4XQ10

© 2017 Microchip Technology Inc.

Product Brief

DS40001920A-page 10