ELECTRICAL CHARACTERISTICS

Power On Reset Section

POR SPECIFICATIONS

Specification Parameter

Required Value

Vcc max undervoltage detect trip point, Vuv

4.06 to 4.3

Vcc trip point hysteresis

1%

Vdd undervoltage detect trip point Vuvd

9.3 to 9.8 volts

Vdd trip point hysteresis

1%

Max POR\ delay timing

100 msecs

Forcing current to reset POR_RC (for in circuit test only)

nominal 1 milliamp

AC UV detection - nondetectable pulse Tuvmin (1)

1

µsec

AC UV detection - detectable pulse Tuvmax (1)

20

µsecs

(1) AC detection test: done on either supply. With either supply at 0.2 volts above the trip point, a 1.2 volt negative pulse is applied.

Chip must not respond to pulse width of Tuvmin, and must respond to Tuvmax.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

POR\@25°C (7)

1.3

2.0

V

Timing Cap timeout threshold

V

Timing Cap threshold

(10)

POR\ pulse strech width

5

40

100

ms (5)

POR\ pulse tolerance

±20%

(6)

external POR\ input required

pulse width

300

ns (9)

Voltage measurement point for

Tpmin

0.8

V

Pullup Current, POR\, steady

state (at 3V)

100

µA

Rise time on POR\, internal

driver with 100pF load (2)

100

ns

Pullup Current, POR\,

momentary

3.2

mA

Notes:

(1) dVmarg% The margining limit is determined as a fraction of the actual chip margin circuitry.

(2) hysteresis on POR\ is optional.

Load: POR\ will see approximately 90 pF plus an external pullup source of approximately 6k ohms. No external bulk capacitance is used

on POR\.

(3) fall time measured from 2 volts to 0.8 volts.

(4) pulse width measured from Vporint volts on falling edge to 1.6 volts on rising edge.

(5) is capable of meeting this timing with a 0.1

µF or less, 20% tolerance ceramic capacitor. Nominal design point, .047µF is 40 ms ±20%.

(6) Timing tolerance on POR pulse width irrespective of external parts.

(7) POR\ is valid if either Vcc or Vdd exceeds this voltage.

(8,9) Tpmin acc is the minimum POR\ pulse width which the combo must recognize as a valid external POR. This corresponds to the width of

the reset pulse from the processor. Pulse widths narrower than this may or may not be recognized. Tpmin rej is the value of pulse width

above which the combo should not recognize a pulse.

in order to prevent deadly embrace with the microprocessor. The specified value is needed with 3.3V logic circuitry.

L6256

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