L6256 datasheet(10/28 Pages) STMICROELECTRONICS

10 / 28 page

Protocol (general):

This protocol is part of a multiple chip protocol

which affects several different Western Digital

chip specifications. Changes to this protocol will

affect several vendors.

Specifications for this chip conform to the timing

specification

The serial protocol used to communicate with the

chip is based on a fixed length 2 byte write or 3

byte read cycle (packets). Each packet sent to

the chip is qualified by Dolphin chi select and by

the address section of the first byte sent to the

chip (bits transferred on clock cycles 2 through 4).

The R/W bit determines packet length and bus di-

rection.

At the end of the 16th bit (write) the data is trans-

ferred to the appropriate registers.

At the end of the 8th (read) bit, the internally ad-

dressed registers is ready to be placed on the se-

rial bus. A dead bit is provided in all cases as the

first bit read back from the Dolphin, to allow inter-

nal propagation delays and to provide for use of

the clock to gate data into the internal shift regis-

ter. At high data rates the processor has to insert

some time in order to turn the bus around from

write to read mode.

Multiple packets can be sent back to back without

a dead space in between when other chips are

addressed (except for the specified clock cycles

inserted by the processor hardware). The chip is

able to decode this case.

At high data rates, a dead space of at least 1

clock cycle must be allowed in between bytes of

the packet for propagation delays internally.

tfall

VCC

Vmin

Vtcap

POR\

Vccmin

Vtcap

Vcth

Internal POR

tpmin

tstretch

Vmin

Vlw

Vporint

D97IN587

Figure 4: Power On Reset Waveforms and Timing

Thermal Shutdown Section

Symbol

Parameter

Value

Unit

THlimit

Thermal Shutdown Die Temperature (1)

±5 above Thwarn

°C

Thhyst

Thermal Shutdown Hysteresis (1)

°C

Thwarn

Thermal Warning (1)

145

±15

°C

(1) Guaranteed by design

SERIAL PORT SECTION

General Specification

Data rate

6 to 12.5MHz

Clock Byte Synchronization

internal

Max load to external parts

15pF

Max external load

5mA or 1.2K pullup

Max bus load capacitance

60pF

Output Drive Structure

3 state, active high and

low (not open drain)

Min Speed without dead bit

7MHz (see timing

section) (1)

Internal pullup resistor

none

(1) Clock duty cycle of 40% to 60%

L6256

10/28

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