PCI11010C datasheet(3/46 Pages) MICROCHIP

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2025 Microchip Technology Inc. and its subsidiaries

DS00006232A-page 3

PCI11010C

1.0

PREFACE

• Section 1.1, "General Terms"

• Section 1.2, "Buffer Types"

• Section 1.3, "Pin Reset States"

• Section 1.4, "Reference Documents"

1.1

General Terms

TABLE 1-1:

GENERAL TERMS

Term

Description

AFE

Analogue Front End (AFE)

Bandwidth

Bandwidth is defined as the rate of data transfer, bit rate or throughput.

CC is an abbreviation for Configuration Channel. This is used in the discovery, configuration and

management of connections across a cable.

CDM

CDM is an abbreviation for Charge Device Model. This is a Model of ESD caused by mechanical

handling. See [JS-002-2014].

Completion

In PCIe Completion refers to the Packet used to terminate, or to partially terminate, a transaction

sequence. A Completion always corresponds to a preceding Request, and, in some cases,

includes data.

See [PCIe5].

Configuration Request Retry

Status

For PCI Configuration Requests only, following reset it is possible for a device to terminate the

request but indicate that it is temporarily unable to process the Request, but will be able to

process the PCI Configuration Request in the future - in this case, the Configuration Request

Retry Status (CRS) Completion Status is used.

See [PCIe5].

Configuration Space

One of the four address spaces within the PCI Express architecture. Packets with a

Configuration Space address are used to configure Physical Functions.

See [PCIe5].

CPU

CPU is an abbreviation for Central Processing Unit. This is the main processor for the system.

Note: In this case, the CPU is located on the Host system and not in the device itself which

has no CPU.

CRS

CRS is an abbreviation for Configuration Request Retry Status.

DFP

DFP is an abbreviation for Downward Facing Port. This is a Port typically used to connect

devices/peripherals (e.g. for USB or PCIe).

Debouncer

A Debouncer is a piece of hardware where the signal is passed through if it is stable for longer

than a Debouncer period.

Direct Memory Access

Direct Memory Access is a feature of computer systems that allows certain hardware

subsystems to access main system memory (RAM) independently of the central processing unit

(CPU). With DMA, the CPU first initiates the transfer, then it does other operations while the

transfer is in progress, and it finally receives an interrupt from the DMA Controller (DMAC) when

the operation is done.

DMA

DMA is an abbreviation for Direct Memory Access.

DMAC

DMAC is an abbreviation for DMA Controller.

DMA Controller

A DMA Controller is a hardware device that allows I/O devices to directly access memory with

less participation from the processor.

EEPROM

EEPROM is an abbreviation for Electrically Erasable Programmable Read-only Memory.

EEPROM I²C Controller

The EEPROM I²C Controller is used to read and write EEPROMs via I²C.

ESD

ESD is an abbreviation for Electro-static Discharge.

FCS

FCS is an abbreviation for Frame Check Sequence.

FET

FET is an abbreviation for Field Effect Transistor. This is typically used to switch on/off power.

GPIO

GPIO is an abbreviation for General Programmable I/O. It is used to refer to PIO accessible

externally to the part. Since there is no internal PIO used in the device the terms PIO and GPIO

have been used interchangeably.

HBM

HBM is an abbreviation for Human Body Model. The HBM simulates ESD from humans. See

[JESD22-A115C].

Hot-Plug

In PCI Hot-Plug is the insertion and removal of add-in cards without powering down the Platform

or restarting the operating system from a specific Hot-Plug slot.

See [PCIHotPlug].

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