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PCI11010C Datasheet(PDF) 14 Page - Microchip Technology

Part # PCI11010C
Description  PCIe Switch with Integrated Ethernet MAC and Programmable I/O
PDF  46 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PCI11010C Datasheet(HTML) 14 Page - Microchip Technology

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2025 Microchip Technology Inc. and its subsidiaries
DS00006232A-page 14
PCI11010C
3.1
Pin Descriptions
TABLE 3-2:
PIN DESCRIPTIONS
Name
Symbol
Buffer Type
Description
PCIe Common Pins
PCIe REFCLK+
Input
PCIE_REFCLK_IN_P
LVDS
Common PCIe REFCLK+ input from host
PCIe REFCLK-
Input
PCIE_REFCLK_IN_M
LVDS
Common PCIe REFCLK- input from host
PCIe Reset#
Input
PCIE_PERST_N
IS
Power and Clock Good Indication
The PERST# signal indicated that both PCIe power
and clock are available.
This active low signal is used by the system to reset
the chip. The active low pulse should be at least 1 µs
wide.
Note: When the device is powered down, this pin is
isolated from the PCIe bus and does not pres-
ent any significant loading or provide any
drive.
PCIe Port 0 (Upstream) Pins
PCIe TX+
Lane 0 Port 0
PCIE_TXP_L0_P0
I/O-P
Upstream PCIe Port 0 Lane 0 TX+
PCIe TX-
Lane 0 Port 0
PCIE_TXM_L0_P0
I/O-P
Upstream PCIe Port 0 Lane 0 TX-
PCIe RX+
Lane 0 Port 0
PCIE_RXP_L0_P0
I/O-P
Upstream PCIe Port 0 Lane 0 RX+
PCIe RX-
Lane 0 Port 0
PCIE_RXM_L0_P0
I/O-P
Upstream PCIe Port 0 Lane 0 RX-
PCIe TX+
Lane 1 Port 0
PCIE_TXP_L1_P0
I/O-P
Upstream PCIe Port 0 Lane 1 TX+
PCIe TX-
Lane 1 Port 0
PCIE_TXM_L1_P0
I/O-P
Upstream PCIe Port 0 Lane 1 TX-
PCIe RX+
Lane 1 Port 0
PCIE_RXP_L1_P0
I/O-P
Upstream PCIe Port 0 Lane 1 RX+
PCIe RX-
Lane 1 Port 0
PCIE_RXM_L1_P0
I/O-P
Upstream PCIe Port 0 Lane 1 RX-
PCIe Port 1 (Downstream) Pins
PCIe TX+
Lane 0 Port 1
PCIE_TXP_L0_P1
I/O-P
Downstream PCIe Port 1 Lane 0 TX+
PCIe TX-
Lane 0 Port 1
PCIE_TXM_L0_P1
I/O-P
Downstream PCIe Port 1 Lane 0 TX-
PCIe RX+
Lane 0 Port 1
PCIE_RXP_L0_P1
I/O-P
Downstream PCIe Port 1 Lane 0 RX+



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