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STA333W

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7.6

Variable distortion compensation registers (addresses 0x29 -

0x2A)

DCC bits determine the 16 MSBs of the Distortion compensation coefficient. This coefficient

is used in place of the default coefficient when DCCV = 1.

7.6.1

Variable distortion compensation register (bits [15:8])

7.6.2

Variable distortion compensation register (bits [7:0])

7.7

Fault detect recovery constant registers (addresses 0x2B -

0x2C)

FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the

TRISTATE output will be immediately asserted low and held low for the time period specified

by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The

default value of 0x000C specifies approximately 0.1 ms.

7.7.1

Fault detect recovery constant register (bits [15:8])

7.7.2

Fault detect recovery constant register (bits [7:0])

DCC15

DCC14

DCC13

DCC12

DCC11

DCC10

DCC9

DCC8

DCC7

DCC6

DCC5

DCC4

DCC3

DCC2

DCC1

DCC0

FDRC15

FDRC14

FDRC13

FDRC12

FDRC11

FDRC10

FDRC9

FDRC8

FDRC7

FDRC6

FDRC5

FDRC4

FDRC3

FDRC2

FDRC1

FDRC0

00001100

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