AM2431BSDGHIALVR. datasheet(133/282 Pages) TI2

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6.11.3.3 Clock Timing

Tables and figures provided in this section define timing conditions, timing requirements, and switching

characteristics for clock signals.

Table 6-19. Clock Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.5

V/ns

OUTPUT CONDITIONS

Output load capacitance

10ns ≤ tc < 20ns

10 pF

20ns ≤ tc

30 pF

Table 6-20. Clock Timing Requirements

see Figure 6-14

NO.

MIN

MAX UNIT

CLK1

tc(EXT_REFCLK1)

Cycle time minimum, EXT_REFCLK1

CLK2

tw(EXT_REFCLK1H)

Pulse Duration, EXT_REFCLK1 high

E*0.45(1)

E*0.55(1)

CLK3

tw(EXT_REFCLK1L)

Pulse Duration, EXT_REFCLK1 low

E*0.45(1)

E*0.55(1)

CLK1

tc(MCU_EXT_REFCLK0)

Cycle time minimum, MCU_EXT_REFCLK0

CLK2

tw(MCU_EXT_REFCLK0H)

Pulse Duration, MCU_EXT_REFCLK0 high

F*0.45(2)

F*0.55(2)

CLK3

tw(MCU_EXT_REFCLK0L)

Pulse Duration, MCU_EXT_REFCLK0 low

F*0.45(2)

F*0.55(2)

(1)

E = EXT_REFCLK1 cycle time

(2)

F = MCU_EXT_REFCLK0 cycle time

Input Clock

CLK1

CLK2

CLK3

Figure 6-14. Clock Timing Requirements

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AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

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