AM2431BSDGHIALVR. datasheet(176/282 Pages) TI2

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6.11.5.8.3 GPMC and NAND Flash — Asynchronous Mode

Table 6-62 and Table 6-63 present timing requirements and switching characteristics for GPMC and NAND Flash

— Asynchronous Mode.

Table 6-62. GPMC and NAND Flash Timing Requirements – Asynchronous Mode

see Figure 6-52

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

GNF12(1)

tacc(d)

Access time, input data GPMC_AD[15:0](3)

J(2)

(1)

The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the

active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.

(2)

J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)

(3)

GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

Table 6-63. GPMC and NAND Flash Switching Characteristics – Asynchronous Mode

see Figure 6-50, Figure 6-51, Figure 6-52 and Figure 6-53

NO.

PARAMETER

MIN

MAX

UNIT

GNF0

tw(wenV)

Pulse duration, output write enable GPMC_WEn valid

A(1)

GNF1

td(csnV-wenV)

Delay time, output chip select GPMC_CSn[i](13) valid to output write

enable GPMC_WEn valid

B(2) - 2

B(2) + 2

GNF2

tw(cleH-wenV)

Delay time, output lower-byte enable and command latch enable

GPMC_BE0n_CLE high to output write enable GPMC_WEn valid

C(3) - 2

C(3) + 2

GNF3

tw(wenV-dV)

Delay time, output data GPMC_AD[15:0] valid to output write

enable GPMC_WEn valid

D(4) - 2

D(4) + 2

GNF4

tw(wenIV-dIV)

Delay time, output write enable GPMC_WEn invalid to output data

GPMC_AD[15:0] invalid

E(5) - 2

E(5) + 2

GNF5

tw(wenIV-cleIV)

Delay time, output write enable GPMC_WEn invalid to output

lower-byte enable and command latch enable GPMC_BE0n_CLE

invalid

F(6) - 2

F(6) + 2

GNF6

tw(wenIV-CSn[i]V)

Delay time, output write enable GPMC_WEn invalid to output chip

select GPMC_CSn[i](13) invalid

G(7) - 2

G(7) + 2

GNF7

tw(aleH-wenV)

Delay time, output address valid and address latch enable

GPMC_ADVn_ALE high to output write enable GPMC_WEn valid

C(3) - 2

C(3) + 2

GNF8

tw(wenIV-aleIV)

Delay time, output write enable GPMC_WEn invalid to output

address valid and address latch enable GPMC_ADVn_ALE invalid

F(6) - 2

F(6) + 2

GNF9

tc(wen)

Cycle time, write

H(8)

GNF10

td(csnV-oenV)

Delay time, output chip select GPMC_CSn[i](13) valid to output

enable GPMC_OEn_REn valid

I(9) - 2

I(9) + 2

GNF13

tw(oenV)

Pulse duration, output enable GPMC_OEn_REn valid

K(10)

GNF14

tc(oen)

Cycle time, read

L(11)

GNF15

tw(oenIV-CSn[i]V)

Delay time, output enable GPMC_OEn_REn invalid to output chip

select GPMC_CSn[i](13) invalid

M(12) - 2

M(12) + 2

(1)

A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

(2)

B = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)

(3)

C = ((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay)) × GPMC_FCLK(14) Note: For

DeviceType: NAND

•

During Command Latch Cycle: CLE signal is controlled by the ADVOnTime and ADVWrOffTime timing parameters

•

During Address Latch Cycle: ALE signal is controlled by the ADVOnTime and ADVWrOffTime timing parameters.

(4)

D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14)

(5)

E = ((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK(14)

(6)

F = ((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay)) × GPMC_FCLK(14) Note:

For DeviceType: NAND

•

During Command Latch Cycle: CLE signal is controlled by the ADVOnTime and ADVWrOffTime timing parameters

•

During Address Latch Cycle: ALE signal is controlled by the ADVOnTime and ADVWrOffTime timing parameters.

(7)

G = ((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)

(8)

H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)

AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

www.ti.com

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