AM2431BSDGHIALVR. datasheet(177/282 Pages) TI2

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(9)

I = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)

(10) K = (OEOffTime - OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14)

(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)

(12) M = ((CSRdOffTime - OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - OEExtraDelay)) × GPMC_FCLK(14)

(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

GPMC_FCLK

GPMC_CSn[i]

GPMC_BE0n_CLE

GPMC_ADCn_ALE

GPMC_OEn_REn

GPMC_WEn

GPMC_AD[15:0]

Command

GNF0

GNF1

GNF2

GNF3

GNF4

GNF5

GNF6

GPMC_12

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

Figure 6-50. GPMC and NAND Flash — Command Latch Cycle

GPMC_FCLK

GPMC_CSn[i]

GPMC_BE0n_CLE

GPMC_ADVn_ALE

GPMC_OEn_REn

GPMC_WEn

GPMC_AD[15:0]

Address

GNF0

GNF1

GNF7

GNF3

GNF4

GNF6

GNF8

GNF9

GPMC_13

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

Figure 6-51. GPMC and NAND Flash — Address Latch Cycle

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AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

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AM2431BSDGHIALVR. Datasheet(PDF) 177 Page - Texas Instruments

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