AM2431BSDGHIALVR. datasheet(189/282 Pages) TI2

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6.11.5.12 MMCSD

The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),

and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at

transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking

for syntactical correctness.

For more details about MMCSD interfaces, see the corresponding MMC0 and MMC1 subsections within Signal

Descriptions and Detailed Description sections.

Note

Some operating modes require software configuration of the MMC DLL delay settings, as shown in

Table 6-72 and Table 6-82.

The modes which show a value of "Tuning" in the ITAPDLYSEL column of Table 6-72 and Table 6-82

require a tuning algorithm to be used for optimizing input timing. Refer to the MMCSD Programming

Guide in the device TRM for more information on the tuning algorithm and configuration of input

delays required to optimize input timing.

For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in

the device TRM.

6.11.5.12.1 MMC0 - eMMC Interface

MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and supports the

following eMMC applications:

• Legacy speed

• High speed SDR

• High speed DDR

• HS200

Table 6-72 presents the required DLL software configuration settings for MMC0 timing modes.

Table 6-72. MMC0 DLL Delay Mapping for all Timing Modes

MMCSD0_MMC_SSCFG_PHY_CTRL_x_REG

x = 1

x = 4

x = 5

BIT FIELD

[1]

[31:24]

[20]

[15:12]

[8]

[4:0]

[17:16]

[10:8]

[2:0]

BIT FIELD NAME

ENDLL

STRBSEL

OTAPDLYENA

OTAPDLYSEL

ITAPDLYENA

ITAPDLYSEL

SELDLYTXCLK

SELDLYRXCLK

FRQSEL

CLKBUFSEL

MODE

DESCRIPTION

ENABLE

DLL

STROBE

DELAY

OUTPUT

DELAY

ENABLE

OUTPUT

DELAY

VALUE

INPUT

DELAY

ENABLE

INPUT

DELAY

VALUE

DLL

DELAY CHAIN

SELECT

DLL REF

FREQUENCY

DELAY

BUFFER

DURATION

Legacy

SDR

8-bit PHY

operating

1.8V, 25MHz

0x0

NA(1)

0x1

0x10

0x1

0x3(2)

NA(3)

0x7

High

Speed

SDR

8-bit PHY

operating

1.8V, 50MHz

0x0

NA(1)

0x1

0xA

0x1

0x3(2)

NA(3)

0x7

High

Speed

DDR

8-bit PHY

operating

1.8V, 50MHz

0x1

0x0

0x1

0x6

0x1

0x3

0x0

0x4

NA(4)

HS200

8-bit PHY

operating

1.8V, 200MHz

0x1

0x0

0x1

0x7

0x1

Tuning(5)

0x0

NA(4)

(1)

NA means this register field has no function when operating with half-cycle timing, which is required for this mode.

(2)

The SELDLYTXCLK bit has no function when operating with half-cycle timing, which is required for this mode.

(3)

NA means this register field has no function when ENDLL is set to 0x0.

(4)

NA means this register field has no function when ENDLL is set to 0x1.

(5)

Tuning means this mode requires a tuning algorithm to be used to determine optimal input timing

Table 6-73 presents timing conditions for MMC0.

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SPRSP65J – APRIL 2021 – REVISED JUNE 2026

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