AM2431BSDGHIALVR. datasheet(191/282 Pages) TI2

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6.11.5.12.1.1 Legacy SDR Mode

Table 6-74, Figure 6-58, Table 6-75, and Figure 6-59 present timing requirements and switching characteristics

for MMC0 – Legacy SDR Mode.

Table 6-74. MMC0 Timing Requirements – Legacy SDR Mode

see Figure 6-58

NO.

MIN

MAX

UNIT

LSDR1

tsu(cmdV-clkH)

Setup time, MMC0_CMD valid before MMC0_CLK rising edge

1.56

LSDR2

th(clkH-cmdV)

Hold time, MMC0_CMD valid after MMC0_CLK rising edge

5.44

LSDR3

tsu(dV-clkH)

Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge

1.56

LSDR4

th(clkH-dV)

Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge

5.44

Figure 6-58. MMC0 – Legacy SDR – Receive Mode

Table 6-75. MMC0 Switching Characteristics – Legacy SDR Mode

see Figure 6-59

NO.

PARAMETER

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

LSDR5

tc(clk)

Cycle time, MMC0_CLK

LSDR6

tw(clkH)

Pulse duration, MMC0_CLK high

18.7

LSDR7

tw(clkL)

Pulse duration, MMC0_CLK low

18.7

LSDR8

td(clkL-cmdV)

Delay time, MMC0_CLK falling edge to MMC0_CMD transition

-2.3

2.9

LSDR9

td(clkL-dV)

Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition

-2.3

2.9

Figure 6-59. MMC0 – Legacy SDR – Transmit Mode

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AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

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