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AM2431BSDGHIALVR. Datasheet(PDF) 195 Page - Texas Instruments

Part # AM2431BSDGHIALVR.
Description  AM243x Sitara™ Microcontrollers
PDF  282 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

AM2431BSDGHIALVR. Datasheet(HTML) 195 Page - Texas Instruments

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6.11.5.12.2 MMC1 - SD/SDIO Interface
MMC1 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer
Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:
• Default speed
• High speed
• UHS–I SDR12
• UHS–I SDR25
• UHS–I SDR50
• UHS–I SDR104
• UHS–I DDR50
Table 6-82 presents the required DLL software configuration settings for MMC1 timing modes.
Table 6-82. MMC1 DLL Delay Mapping for all Timing Modes
REGISTER NAME
MMCSD1_MMC_SSCFG_PHY_CTRL_4_REG
BIT FIELD
[20]
[15:12]
[8]
[4:0]
BIT FIELD NAME
OTAPDLYENA
OTAPDLYSEL
ITAPDLYENA
ITAPDLYSEL
MODE
DESCRIPTION
DELAY
ENABLE
DELAY
VALUE
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
Default
Speed
4-bit PHY
operating
3.3V, 25MHz
NA(1)
NA(1)
0x1
0x0
High
Speed
4-bit PHY
operating
3.3V, 50MHz
NA(1)
NA(1)
0x1
0x0
UHS-I
SDR12
4-bit PHY
operating
1.8V, 25MHz
0x1
0xF
0x1
0x0
UHS-I
SDR25
4-bit PHY
operating
1.8V, 50MHz
0x1
0xF
0x1
0x0
UHS-I
SDR50
4-bit PHY
operating
1.8V, 100MHz
0x1
0xC
0x1
Tuning(2)
UHS-I
DDR50
4-bit PHY
operating
1.8V, 50MHz
0x1
0x9
0x1
Tuning(2)
UHS-I
SDR104
4-bit PHY
operating
1.8V 200MHz
0x1
0x6
0x1
Tuning(2)
(1)
NA means this register field has no function when operating with half-cycle timing, which is required for this mode.
(2)
Tuning means this mode requires a tuning algorithm to be used to determine optimal input timing
Table 6-83 presents timing conditions for MMC1.
www.ti.com
AM2434, AM2432, AM2431
SPRSP65J – APRIL 2021 – REVISED JUNE 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: AM2434 AM2432 AM2431



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