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AM2431BSDGHIALVR. Datasheet(PDF) 199 Page - Texas Instruments

Part # AM2431BSDGHIALVR.
Description  AM243x Sitara™ Microcontrollers
PDF  282 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

AM2431BSDGHIALVR. Datasheet(HTML) 199 Page - Texas Instruments

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6.11.5.12.2.3 UHS–I SDR12 Mode
Table 6-88, Figure 6-70, Table 6-89, and Figure 6-71 present timing requirements and switching characteristics
for MMC1 – UHS-I SDR12 Mode.
Table 6-88. Timing Requirements for MMC1 – UHS-I SDR12 Mode
see Figure 6-70
NO.
MIN
MAX
UNIT
SDR121
tsu(cmdV-clkH)
Setup time, MMC1_CMD valid before MMC1_CLK rising edge
2.35
ns
SDR122
th(clkH-cmdV)
Hold time, MMC1_CMD valid after MMC1_CLK rising edge
1.67
ns
SDR123
tsu(dV-clkH)
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge
2.35
ns
SDR124
th(clkH-dV)
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge
1.67
ns
MMC[ ]_CMD
x
MMC
DAT
[ ]_
[3:0]
x
SDR121
SDR122
SDR123
SDR124
MMC[ ]_CLK
x
Figure 6-70. MMC1 – UHS-I SDR12 – Receive Mode
Table 6-89. Switching Characteristics for MMC1 – UHS-I SDR12 Mode
see Figure 6-71
NO.
PARAMETER
MIN
MAX
UNIT
fop(clk)
Operating frequency, MMC1_CLK
25
MHz
SDR125
tc(clk)
Cycle time, MMC1_CLK
40
ns
SDR126
tw(clkH)
Pulse duration, MMC1_CLK high
18.7
ns
SDR127
tw(clkL)
Pulse duration, MMC1_CLK low
18.7
ns
SDR128
td(clkL-cmdV)
Delay time, MMC1_CLK rising edge to MMC1_CMD transition
1.2
8
ns
SDR129
td(clkL-dV)
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition
1.2
8
ns
MMC[ ]_CLK
x
MMC
CMD
[ ]_
x
MMC
DAT
[ ]_
[3:0]
x
SDR125
SDR127
SDR126
SDR128
SDR129
SDR128
SDR129
Figure 6-71. MMC1 – UHS-I SDR12 – Transmit Mode
www.ti.com
AM2434, AM2432, AM2431
SPRSP65J – APRIL 2021 – REVISED JUNE 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: AM2434 AM2432 AM2431



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