AM2431BSDGHIALVR. datasheet(207/282 Pages) TI2

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6.11.5.14.1 OSPI0 PHY Mode

6.11.5.14.1.1 OSPI0 With PHY Data Training

Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating

frequency. A data training method may be implemented to dynamically configure optimal read and write timing.

Implementing data training enables proper operation across temperature with a specific process, voltage, and

frequency operating condition, while achieving a higher operating frequency.

Data transmit and receive timing parameters are not defined for the data training use case since they are

dynamically adjusted based on the operating condition.

Table 6-99 defines DLL delays required for OSPI0 with Data Training. Table 6-100, Figure 6-79, Table 6-101, and

Figure 6-80 present timing requirements and switching characteristics for OSPI0 with Data Training.

Table 6-99. OSPI0 DLL Delay Mapping for PHY Data Training

MODE

DELAY VALUE

OSPI_PHY_CONFIGURATION_REG

Transmit

All modes

PHY_CONFIG_TX_DLL_DELAY_FLD

(1)

Receive

All modes

PHY_CONFIG_RX_DLL_DELAY_FLD

(2)

PHY_MASTER_CONTROL_REG

All modes

PHY_MASTER_PHASE_DETECT_SELECTOR_FLD

0x3

(1)

Transmit DLL delay value determined by training software

(2)

Receive DLL delay value determined by training software

Table 6-100. OSPI0 Timing Requirements – PHY Data Training

see Figure 6-79

NO.

MODE

MIN

MAX

UNIT

O15

tsu(D-LBCLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_DQS edge

DDR with DQS

(1)

O16

th(LBCLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_DQS edge

DDR with DQS

(1)

Minimum setup and hold time requirements for OSPI0_D[7:0] inputs are not defined when Data Training is used to find the optimum

data valid window.

OSPI_DQS

O16

O15

OSPI_TIMING_04

OSPI_D[i:0]

O16

O15

Figure 6-79. OSPI0 Timing Requirements – PHY Data Training, DDR with DQS

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AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

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